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公开(公告)号：US10462391B2
公开(公告)日：2019-10-29
申请号：US15210056
申请日：2016-07-14
发明人： Yung-Ho Alex Chuang , David L. Brown , Devis Contarato , John Fielden , Daniel I. Kavaldjiev , Guoheng Zhao , Jehn-Huar Chern , Guowu Zheng , Donald W. Pettibone , Stephen Biellak
IPC分类号： H04N5/335 , G01N21/95 , G06T7/00 , H04N5/225 , H04N5/347 , H04N5/378 , H04N5/3745 , H04N5/376 , G01N21/956
摘要： An inspection system and methods in which analog image data values (charges) captured by an image sensor are binned (combined) before or while being transmitted as output signals on the image sensor's output sensing nodes (floating diffusions), and in which an ADC is controlled to sequentially generate multiple corresponding digital image data values between each reset of the output sensing nodes. According to an output binning method, the image sensor is driven to sequentially transfer multiple charges onto the output sensing nodes between each reset, and the ADC is controlled to convert the incrementally increasing output signal after each charge is transferred onto the output sensing node. According to a multi-sampling method, multiple charges are vertically or horizontally binned (summed/combined) before being transferred onto the output sensing node, and the ADC samples each corresponding output signal multiple times. The output binning and multi-sampling methods may be combined.
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公开(公告)号：US09658170B2
公开(公告)日：2017-05-23
申请号：US14308383
申请日：2014-06-18
CPC分类号： G01N21/9501 , H04N5/37206 , H04N5/378
摘要： A Time Delay and Integration (TDI) imaging system utilizing variable voltage readout clock signals having progressively increasing amplitudes defined as a function of pixel row location, where pixel rows positioned to receive/collect/transfer image-related charges at the start of the TDI imaging process are controlled using lower amplitude readout clock signals than pixel rows positioned to receive/collect/transfer image-related charges near the end of the TDI process. The clock signal amplitude for each pixel row is determined by the expected maximum amplitude needed to hold and transfer image charges by the pixels of that row. Multiple (e.g., three) primary phase signals are generated that are passed through splitters to provide multiple identical secondary phase signals, and then drivers having gain control circuitry are utilized to produce voltage readout clock signals having the same phases as the primary phase signals, but having two or more different voltage amplitudes.
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3.发明授权Integrated multi-channel analog front end and digitizer for high speed imaging applications 有权集成多通道模拟前端和数字化仪，用于高速成像应用公开(公告)号：US09462206B2
公开(公告)日：2016-10-04
申请号：US14272454
申请日：2014-05-07
发明人： David L. Brown , Mansour Kermat , Lance Glasser , Henrik Nielsen , Guowu Zheng , Kurt Lehman , Kenneth F. Hatch , Yung-Ho Chuang , Venkatraman Iyer
CPC分类号： H04N5/378 , H01L27/14634 , H04N5/3694 , H04N5/37206 , H04N5/37213
摘要： A module for high speed image processing includes an image sensor for generating a plurality of analog outputs representing an image and a plurality of HDDs for concurrently processing the plurality of analog outputs. Each HDD is an integrated circuit configured to process in parallel a predetermined set of the analog outputs. Each channel of the HDD can include an AFE for conditioning a signal representing one sensor analog output, an ADC for converting a conditioned signal into a digital signal, and a data formatting block for calibrations and formatting the digital signal for transport to an off-chip device. The HDDs and drive electronics are combined with the image sensor into one package to optimize signal integrity and high dynamic range, and to achieve high data rates through use of synchronized HDD channels. Combining multiple modules results in a highly scalable imaging subsystem optimized for inspection and metrology applications.
摘要翻译： 用于高速图像处理的模块包括用于产生表示图像的多个模拟输出的图像传感器和用于同时处理多个模拟输出的多个HDD。 每个HDD是被配置为并行处理预定的一组模拟输出的集成电路。 HDD的每个通道可以包括用于调节表示一个传感器模拟输出的信号的AFE，用于将经调节的信号转换成数字信号的ADC，以及用于校准和格式化数字信号以传送到芯片外的数据格式化块 设备。 HDD和驱动电子设备与图像传感器组合成一个封装，以优化信号完整性和高动态范围，并通过使用同步的HDD通道实现高数据速率。 组合多个模块可实现高度可扩展的成像子系统，以优化检测和计量应用。
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公开(公告)号：US20150002655A1
公开(公告)日：2015-01-01
申请号：US14308383
申请日：2014-06-18
CPC分类号： G01N21/9501 , H04N5/37206 , H04N5/378
摘要： A Time Delay and Integration (TDI) imaging system utilizing variable voltage readout clock signals having progressively increasing amplitudes defined as a function of pixel row location, where pixel rows positioned to receive/collect/transfer image-related charges at the start of the TDI imaging process are controlled using lower amplitude readout clock signals than pixel rows positioned to receive/collect/transfer image-related charges near the end of the TDI process. The clock signal amplitude for each pixel row is determined by the expected maximum amplitude needed to hold and transfer image charges by the pixels of that row. Multiple (e.g., three) primary phase signals are generated that are passed through splitters to provide multiple identical secondary phase signals, and then drivers having gain control circuitry are utilized to produce voltage readout clock signals having the same phases as the primary phase signals, but having two or more different voltage amplitudes.
摘要翻译： 时间延迟和积分（TDI）成像系统利用具有逐渐增加的幅度的可变电压读出时钟信号，该幅度被定义为像素行位置的函数，其中像素行被定位为在TDI成像开始时接收/传送图像相关电荷 使用较低幅度读出时钟信号控制处理，该像素行位于与TDI处理结束附近接收/传送/传送图像相关电荷的像素行。 每个像素行的时钟信号幅度由通过该行的像素保持和传送图像电荷所需的预期最大幅度确定。 产生多个（例如三个）主相位信号，其通过分离器传递以提供多个相同的次级相位信号，然后利用具有增益控制电路的驱动器产生具有与主相位信号相同相位的电压读出时钟信号，但是 具有两个或更多个不同的电压幅度。
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公开(公告)号：US20170048467A1
公开(公告)日：2017-02-16
申请号：US15210056
申请日：2016-07-14
发明人： Yung-Ho Alex Chuang , David L. Brown , Devis Contarato , John Fielden , Daniel I. Kavaldjiev , Guoheng Zhao , Jehn-Huar Chern , Guowu Zheng , Donald W. Pettibone , Stephen Biellak
CPC分类号： H04N5/335 , G01N21/9501 , G01N2021/95676 , H04N5/2256 , H04N5/347 , H04N5/3745 , H04N5/3765 , H04N5/378
摘要： An inspection system and methods in which analog image data values (charges) captured by an image sensor are binned (combined) before or while being transmitted as output signals on the image sensor's output sensing nodes (floating diffusions), and in which an ADC is controlled to sequentially generate multiple corresponding digital image data values between each reset of the output sensing nodes. According to an output binning method, the image sensor is driven to sequentially transfer multiple charges onto the output sensing nodes between each reset, and the ADC is controlled to convert the incrementally increasing output signal after each charge is transferred onto the output sensing node. According to a multi-sampling method, multiple charges are vertically or horizontally binned (summed/combined) before being transferred onto the output sensing node, and the ADC samples each corresponding output signal multiple times. The output binning and multi-sampling methods may be combined.
摘要翻译： 一种检查系统和方法，其中由图像传感器捕获的模拟图像数据值（电荷）在作为图像传感器的输出感测节点（浮动扩散）之间的输出信号被发送之前或同时被分组（组合），并且其中ADC是 被控制以在输出感测节点的每个复位之间顺序地生成多个对应的数字图像数据值。 根据输出合并方法，驱动图像传感器以在每个复位之间顺序地将多个电荷传送到输出感测节点上，并且在每个电荷被传送到输出感测节点之后，控制ADC转换递增增加的输出信号。 根据多采样方法，在转移到输出感测节点之前，将多个电荷垂直或水平分类（相加/组合），并且ADC对每个对应的输出信号进行多次采样。 可以组合输出合并和多采样方法。
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6.发明授权Interposer based imaging sensor for high-speed image acquisition and inspection systems 有权基于内插器的成像传感器，用于高速图像采集和检测系统公开(公告)号：US08748828B2
公开(公告)日：2014-06-10
申请号：US13622155
申请日：2012-09-18
发明人： David L. Brown , Guowu Zheng , Yung-Ho Chuang , Venkatraman Iyer
IPC分类号： G01T1/20
CPC分类号： H01L27/14636 , G01N21/9501 , H01L27/14618 , H01L27/14634 , H01L27/1464 , H01L27/14806 , H01L2224/16225 , H01L2924/15311 , H01L2924/19105 , H04N5/3355 , H04N5/369 , H05K13/00 , Y10T29/49117
摘要： The present invention includes an interposer disposed on a surface of a substrate, a light sensing array sensor disposed on the interposer, the light sensing array sensor being back-thinned and configured for back illumination, the light sensing array sensor including columns of pixels, one or more amplification circuitry elements configured to amplify an output of the light sensing array sensor, the amplification circuits being operatively connected to the interposer, one or more analog-to-digital conversion circuitry elements configured to convert an output of the light sensing array sensor to a digital signal, the ADC circuitry elements being operatively connected to the interposer, one or more driver circuitry elements configured to drive a clock or control signal of the array sensor, the interposer configured to electrically couple at least two of the light sensing array sensor, the amplification circuits, the conversion circuits, the driver circuits, or one or more additional circuits.
摘要翻译： 本发明包括设置在基板的表面上的插入器，设置在插入件上的光感测阵列传感器，光感测阵列传感器被背面薄化并被配置为用于背光照明，光感测阵列传感器包括像素列，一 或多个放大电路元件，被配置为放大光感测阵列传感器的输出，放大电路可操作地连接到插入器，一个或多个模拟 - 数字转换电路元件，被配置为将光感测阵列传感器的输出转换成 数字信号，所述ADC电路元件可操作地连接到所述插入器，配置成驱动所述阵列传感器的时钟或控制信号的一个或多个驱动器电路元件，所述插入器被配置为电耦合所述光感测阵列传感器中的至少两个， 放大电路，转换电路，驱动器电路或一个或多个附加电路 电话
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7.发明授权Interposer based imaging sensor for high-speed image acquisition and inspection systems 有权基于内插器的成像传感器，用于高速图像采集和检测系统公开(公告)号：US09299738B1
公开(公告)日：2016-03-29
申请号：US14299749
申请日：2014-06-09
IPC分类号： G01T1/20 , H01L27/146 , H04N5/335
CPC分类号： H01L27/14636 , G01N21/9501 , H01L27/14618 , H01L27/14634 , H01L27/1464 , H01L27/14806 , H01L2224/16225 , H01L2924/15311 , H01L2924/19105 , H04N5/3355 , H04N5/369 , H05K13/00 , Y10T29/49117
摘要： The present invention includes an interposer disposed on a surface of a substrate, a light sensing array sensor disposed on the interposer, the light sensing array sensor being back-thinned and configured for back illumination, the light sensing array sensor including columns of pixels, one or more amplification circuitry elements configured to amplify an output of the light sensing array sensor, the amplification circuits being operatively connected to the interposer, one or more analog-to-digital conversion circuitry elements configured to convert an output of the light sensing array sensor to a digital signal, the ADC circuitry elements being operatively connected to the interposer, one or more driver circuitry elements configured to drive a clock or control signal of the array sensor, the interposer configured to electrically couple at least two of the light sensing array sensor, the amplification circuits, the conversion circuits, the driver circuits, or one or more additional circuits.
摘要翻译： 本发明包括设置在基板的表面上的插入器，设置在插入件上的光感测阵列传感器，光感测阵列传感器被背面薄化并被配置为用于背光照明，光感测阵列传感器包括像素列，一 或多个放大电路元件，被配置为放大光感测阵列传感器的输出，放大电路可操作地连接到插入器，一个或多个模拟 - 数字转换电路元件，被配置为将光感测阵列传感器的输出转换成 数字信号，所述ADC电路元件可操作地连接到所述插入器，配置成驱动所述阵列传感器的时钟或控制信号的一个或多个驱动器电路元件，所述插入器被配置为电耦合所述光感测阵列传感器中的至少两个， 放大电路，转换电路，驱动器电路或一个或多个附加电路 电话
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8.发明申请Integrated Multi-Channel Analog Front End And Digitizer For High Speed Imaging Applications 有权用于高速成像应用的集成多通道模拟前端和数字转换器公开(公告)号：US20140240562A1
公开(公告)日：2014-08-28
申请号：US14272454
申请日：2014-05-07
发明人： David L. Brown , Mansour Kermat , Lance Glasser , Henrik Nielsen , Guowu Zheng , Kurt Lehman , Kenneth F. Hatch , Yung-Ho Chuang , Venkatraman Iyer
IPC分类号： H04N5/378
CPC分类号： H04N5/378 , H01L27/14634 , H04N5/3694 , H04N5/37206 , H04N5/37213
摘要： A module for high speed image processing includes an image sensor for generating a plurality of analog outputs representing an image and a plurality of HDDs for concurrently processing the plurality of analog outputs. Each HDD is an integrated circuit configured to process in parallel a predetermined set of the analog outputs. Each channel of the HDD can include an AFE for conditioning a signal representing one sensor analog output, an ADC for converting a conditioned signal into a digital signal, and a data formatting block for calibrations and formatting the digital signal for transport to an off-chip device. The HDDs and drive electronics are combined with the image sensor into one package to optimize signal integrity and high dynamic range, and to achieve high data rates through use of synchronized HDD channels. Combining multiple modules results in a highly scalable imaging subsystem optimized for inspection and metrology applications.
摘要翻译： 用于高速图像处理的模块包括用于产生表示图像的多个模拟输出的图像传感器和用于同时处理多个模拟输出的多个HDD。 每个HDD是被配置为并行处理预定的一组模拟输出的集成电路。 HDD的每个通道可以包括用于调节表示一个传感器模拟输出的信号的AFE，用于将经调节的信号转换成数字信号的ADC，以及用于校准和格式化数字信号以传送到芯片外的数据格式化块 设备。 HDD和驱动电子设备与图像传感器组合成一个封装，以优化信号完整性和高动态范围，并通过使用同步的HDD通道实现高数据速率。 组合多个模块可实现高度可扩展的成像子系统，以优化检测和计量应用。
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9.发明申请INTERPOSER BASED IMAGING SENSOR FOR HIGH-SPEED IMAGE ACQUISITION AND INSPECTION SYSTEMS 有权用于高速图像采集和检测系统的基于插座的成像传感器公开(公告)号：US20130176552A1
公开(公告)日：2013-07-11
申请号：US13622155
申请日：2012-09-18
发明人： David L. Brown , Guowu Zheng , Yung-Ho Chuang , Venkatraman Iyer
CPC分类号： H01L27/14636 , G01N21/9501 , H01L27/14618 , H01L27/14634 , H01L27/1464 , H01L27/14806 , H01L2224/16225 , H01L2924/15311 , H01L2924/19105 , H04N5/3355 , H04N5/369 , H05K13/00 , Y10T29/49117
摘要： The present invention includes an interposer disposed on a surface of a substrate, a light sensing array sensor disposed on the interposer, the light sensing array sensor being back-thinned and configured for back illumination, the light sensing array sensor including columns of pixels, one or more amplification circuitry elements configured to amplify an output of the light sensing array sensor, the amplification circuits being operatively connected to the interposer, one or more analog-to-digital conversion circuitry elements configured to convert an output of the light sensing array sensor to a digital signal, the ADC circuitry elements being operatively connected to the interposer, one or more driver circuitry elements configured to drive a clock or control signal of the array sensor, the interposer configured to electrically couple at least two of the light sensing array sensor, the amplification circuits, the conversion circuits, the driver circuits, or one or more additional circuits.
摘要翻译： 本发明包括设置在基板的表面上的插入器，设置在插入件上的光感测阵列传感器，光感测阵列传感器被背面薄化并被配置为用于背光照明，光感测阵列传感器包括像素列，一 或多个放大电路元件，被配置为放大光感测阵列传感器的输出，放大电路可操作地连接到插入器，一个或多个模拟 - 数字转换电路元件，被配置为将光感测阵列传感器的输出转换成 数字信号，所述ADC电路元件可操作地连接到所述插入器，配置成驱动所述阵列传感器的时钟或控制信号的一个或多个驱动器电路元件，所述插入器被配置为电耦合所述光感测阵列传感器中的至少两个， 放大电路，转换电路，驱动器电路或一个或多个附加电路 电话
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