公开(公告)号：US20170075578A1

公开(公告)日：2017-03-16

申请号：US14976578

申请日：2015-12-21

Applicant: SK Hynix Inc. ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Gwangsun KIM ,  John Dongjun KIM ,  Yong-Kee KWON

IPC: G06F3/06

Abstract: A memory network includes a first local memory group, a second local memory group, and multiple first channels. The first local memory group includes multiple first memory devices that are not directly connected to each other. The second local memory group includes multiple second memory devices that are not directly connected to each other. The first channels are configured to connect the first memory devices to the second memory devices in a one to one relationship.

Abstract translation: 存储器网络包括第一本地存储器组，第二本地存储器组和多个第一通道。 第一本地存储器组包括彼此不直接相连的多个第一存储器件。 第二本地存储器组包括彼此不直接相连的多个第二存储器件。 第一通道被配置为以一对一关系将第一存储器件连接到第二存储器件。

公开(公告)号：US20160335125A1

公开(公告)日：2016-11-17

申请号：US15146044

申请日：2016-05-04

Applicant: Samsung Electronics Co., Ltd. ,  Korea Advanced Institute of Science and Technology

Inventor： Minseok LEE ,  John Dongjun KIM ,  Woong SEO ,  Soojung RYU ,  Yeongon CHO

IPC: G06F9/50

CPC classification number: G06F9/5038 ,  G06F9/46

Abstract: A processor and corresponding method are described including cores having a thread set allocated based on a pre-set implementation order, and a controller configured to receive scheduling information determined based on an implementation pattern regarding the allocated thread set from one of the cores and transmit the scheduling information to another of the cores. The one of cores determines the scheduling information according to characteristics of an application when implementation of the thread set is completed. Each of the cores re-determines an implementation order regarding the allocated thread set based on the determined scheduling information.

Abstract translation: 描述了一种处理器和相应的方法，其包括具有基于预设实现顺序分配的线程集的核心，以及控制器，被配置为接收基于从一个核心分配的线程集合的实现模式确定的调度信息，并发送 将信息调度到另一个核心。 当线程集合的实现完成时，核心之一根据应用的特性确定调度信息。 每个核心基于所确定的调度信息重新确定关于所分配的线程组的实现顺序。

公开(公告)号：US20180176202A1

公开(公告)日：2018-06-21

申请号：US15704601

申请日：2017-09-14

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

Inventor： Yeonju RO ,  Seongwook JIN ,  Jaehyuk HUH ,  John Dongjun KIM

IPC: H04L29/06 ,  H04W12/04 ,  H04L9/08

CPC classification number: H04L63/067 ,  H04L9/0863 ,  H04L9/3228 ,  H04L63/0428 ,  H04W12/04

Abstract: A device transmits or receives a packet in a memory network including one or more processors and/or one or more memory devices. The device includes a key storage unit configured to store a one-time password (OTP) key that is shared with a target node, an encryption unit configured to encrypt a transmission packet with the OTP key stored in the key storage unit and to transmit the encrypted transmission packet to the target node, and a decryption unit configured to decrypt a receiving packet from the target node with the OTP key stored in the key storage unit. The device is a processor or a memory device in the memory network.

公开(公告)号：US20180173654A1

公开(公告)日：2018-06-21

申请号：US15655671

申请日：2017-07-20

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

Inventor： Byungchul HONG ,  John Dongjun KIM ,  Jungho AHN ,  Yongkee KWON ,  Hongsik KIM

IPC: G06F13/16 ,  G06F12/1009 ,  G06F13/10

CPC classification number: G06F13/1673 ,  G06F12/1009 ,  G06F13/102 ,  G06F2212/154 ,  G06F2212/65

Abstract: A memory device includes a memory cell region including a plurality of memory cells; a memory cell controller configured to control read and write operation for the memory cell region; one or more NDP engines configured to perform a near data processing (NDP) operation for the memory cell region; a command buffer configured to store an NDP command transmitted from a host; and an engine scheduler configured to schedule the NDP operation for the one or more NDP engines according to the NDP command.

公开(公告)号：US20250117323A1

公开(公告)日：2025-04-10

申请号：US18804343

申请日：2024-08-14

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： John Dongjun KIM ,  Jiho KIM

IPC: G06F12/02

Abstract: A flash-based storage device includes a flash memory device including a plurality of flash memory chips connected to a plurality of flash buses, and a storage device controller including a plurality of flash controllers connected to the plurality of flash buses. The plurality of flash buses form a channel supporting packet communication, and each flash controller is implemented to generate a control packet including a command or a data packet including a payload, and transmit packets to a target flash memory chip through the connected flash bus.

公开(公告)号：US20140359335A1

公开(公告)日：2014-12-04

申请号：US14287515

申请日：2014-05-27

Applicant: Samsung Electronics Co., Ltd. ,  Korea Advanced Institute of Science and Technology

Inventor： Woong SEO ,  Yeon-Gon CHO ,  Soo-Jung RYU ,  Seok-Woo SONG ,  John Dongjun KIM ,  Min-Seok LEE

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/4893 ,  Y02D10/171 ,  Y02D10/24

Abstract: A multi-core apparatus includes cores each including an active cycle counting unit configured to store an active cycle count, and a stall cycle counting unit configured to store a stall cycle count. The multi-core apparatus further includes a job scheduler configured to determine an optimal number of cores in an active state based on state information received from each of the cores, and adjust power to maintain the optimal number of cores.

Abstract translation: 多核装置包括各自包括被配置为存储活动周期计数的活动周期计数单元的核，以及配置成存储失速循环计数的失速循环计数单元。 多核装置还包括：作业调度器，被配置为基于从每个核接收到的状态信息来确定活动状态的最佳核数，并调整功率以维持最佳核数。

公开(公告)号：US20140337849A1

公开(公告)日：2014-11-13

申请号：US14276522

申请日：2014-05-13

Applicant: Samsung Electronics Co., Ltd. ,  Korea Advanced Institute of Science and Technology

Inventor： Woong SEO ,  Yeon-Gon CHO ,  Soo-Jung RYU ,  Seok-Woo SONG ,  John Dongjun KIM ,  Min-Seok LEE

IPC: G06F9/46

CPC classification number: G06F9/505 ,  G06F9/46 ,  G06F9/4881 ,  G06F2209/5022

Abstract: An apparatus and a job scheduling method are provided. For example, the apparatus is a multi-core processing apparatus. The apparatus and method minimize performance degradation of a core caused by sharing resources by dynamically managing a maximum number of jobs assigned to each core of the apparatus. The apparatus includes at least one core including an active cycle counting unit configured to store a number of active cycles and a stall cycle counting unit configured to store a number of stall cycles and a job scheduler configured to assign at least one job to each of the at least one core, based on the number of active cycles and the number of stall cycles. When the ratio of the number of stall cycles to a number of active cycles for a core is too great, the job scheduler assigns fewer jobs to that core to improve performance.

Abstract translation: 提供了一种装置和作业调度方法。 例如，该装置是多核处理装置。 该装置和方法通过动态地管理分配给设备的每个核心的最大数量的作业来最小化共享资源所引起的核心性能下降。 所述设备包括至少一个核心，其包括被配置为存储多个活动周期的活动周期计数单元和被配置为存储多个失速周期的失速循环计数单元，以及作业调度器，其被配置为将至少一个作业分配给 至少一个核心，基于活动周期的数量和失速周期的数量。 当停顿周期数与核心的活动周期数之比太大时，作业调度程序为该核心分配较少的作业以提高性能。