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    Unified multi-mode receiver detector
    2.
    发明授权
    Unified multi-mode receiver detector 有权
    统一多模接收机检测器

    公开(公告)号：US08068566B2

    公开(公告)日：2011-11-29

    申请号：US11888228

    申请日：2007-07-31

    Applicant: Raghavan Sudhakar ,  Veerendra Bhora ,  Kamal J. Koshy

    Inventor： Raghavan Sudhakar ,  Veerendra Bhora ,  Kamal J. Koshy

    IPC: H03D1/00

    CPC classification number: H04L5/0023 ,  H04L1/0054 ,  H04L1/0631 ,  H04L1/0643

    Abstract: In general, in one aspect, the disclosure describes a unified simplified maximum likelihood detector to be utilized with multiple input multiple output (MIMO) receivers to estimate transmitted signals. The unified detector includes a common framework capable of being utilized for multiple detection modes and multiple MIMO configurations.

    Abstract translation: 通常，在一个方面，本公开描述了将与多输入多输出（MIMO）接收机一起使用的统一简化最大似然检测器来估计发射信号。 统一检测器包括能够被用于多个检测模式和多个MIMO配置的公共框架。

    Unified multi-mode receiver detector
    3.
    发明申请
    Unified multi-mode receiver detector 有权
    统一多模接收机检测器

    公开(公告)号：US20090034662A1

    公开(公告)日：2009-02-05

    申请号：US11888228

    申请日：2007-07-31

    Applicant: Raghavan Sudhakar ,  Veerendra Bhora ,  Kamal J. Koshy

    Inventor： Raghavan Sudhakar ,  Veerendra Bhora ,  Kamal J. Koshy

    IPC: H03D1/02

    CPC classification number: H04L5/0023 ,  H04L1/0054 ,  H04L1/0631 ,  H04L1/0643

    Abstract: In general, in one aspect, the disclosure describes a unified simplified maximum likelihood detector to be utilized with multiple input multiple output (MIMO) receivers to estimate transmitted signals. The unified detector includes a common framework capable of being utilized for multiple spatial operational modes and multiple MIMO configurations.

    Abstract translation: 通常，在一个方面，本公开描述了将与多输入多输出（MIMO）接收机一起使用的统一简化最大似然检测器来估计发射信号。 统一检测器包括能够用于多个空间操作模式和多个MIMO配置的公共框架。

    Fast CMOS adder with null-carry look-ahead
    6.
    发明授权
    Fast CMOS adder with null-carry look-ahead 有权
    快速CMOS加法器，带空载预读

    公开(公告)号：US06782406B2

    公开(公告)日：2004-08-24

    申请号：US09877805

    申请日：2001-06-07

    Applicant: Kamal J. Koshy

    Inventor： Kamal J. Koshy

    IPC: G06F750

    CPC classification number: G06F7/508

    Abstract: A null-carry-lookahead adder is configured to generate and propagate a null-carry signal within and through blocks and groups of blocks within the adder. The null-carry signal terminates the effects of a carry input signal beyond the point at which the null-carry signal is generated. By forming rules for generating and propagating null-carry signals through blocks and groups of blocks within the adder, a maximum P-channel stack depth of two can be achieved for a four-bit adder block, thereby substantially improving the speed of the null-carry-lookahead adder, compared to a convention carry-lookahead adder that is based on generating and propagating carry signals within the adder.

    Abstract translation: 空进位前瞻加法器被配置为在加法器内部和通过块和块组内生成和传播空进位信号。 空载入信号终止进位输入信号超过产生空进位信号的点的影响。 通过形成用于通过加法器内的块和块组产生和传播空进位信号的规则，对于四位加法器块，可以实现两个最大P信道堆栈深度为2，从而实质上提高零位进位信号的速度， 与前置加法器相比，它是基于在加法器内产生和传播进位信号的惯例进位 - 前瞻加法器。

    QMOS digital logic circuits
    7.
    发明授权
    QMOS digital logic circuits 失效
    QMOS数字逻辑电路

    公开(公告)号：US6130559A

    公开(公告)日：2000-10-10

    申请号：US52768

    申请日：1998-03-31

    Applicant: Poras T. Balsara ,  Kamal J. Koshy

    Inventor： Poras T. Balsara ,  Kamal J. Koshy

    IPC: H03K19/0948 ,  H03K19/10 ,  H03K19/094 ,  H03K19/082

    CPC classification number: B82Y10/00 ,  H03K19/0948 ,  H03K19/10

    Abstract: Circuit designs of basic digital logic gates are disclosed using Resonant Tunneling Diodes (RTDs) and MOSFETs, which reduces the number of devices used for logic design, while exploiting the high speed negative differential resistance (NDR) characteristics of RTDs. Such logic circuits include NAND, NOR, AND, and OR gates and Minority/Majority circuits, which are used in full adder circuits. By implementing RTDs along with conventional MOSFETs, the use of series connected MOSFETs, which results in low output rise and fall times, especially for a large number of inputs, can be avoided. Furthermore, the RTD logic design styles do not require the use of resistors or any elaborate clocking or resetting scheme.

    Abstract translation: 使用谐振隧道二极管（RTD）和MOSFET公开了基本数字逻辑门的电路设计，这减少了用于逻辑设计的器件数量，同时利用RTD的高速负差分电阻（NDR）特性。 这种逻辑电路包括在全加器电路中使用的NAND，NOR，AND和OR门和少数/多数电路。 通过与常规MOSFET一起实施RTD，可以避免使用串联连接的MOSFET，这导致低输出上升和下降时间，特别是对于大量输入。 此外，RTD逻辑设计样式不需要使用电阻或任何精心设计的时钟或复位方案。

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