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1.发明授权System and method for compiling a source code supporting data parallel variables 失效用于编译支持数据并行变量的源代码的系统和方法
公开(公告)号：US5381550A
公开(公告)日：1995-01-10
申请号：US179267
申请日：1994-01-10
摘要： A compiler for compiling a computer program which is adapted for use with a data parallel computer. The compiler supports variables which involve parallelism. Variables which involve parallelism are parallel variables, templates for parallel variables called shapes, and pointers to parallel variables. For each variable involving parallelism declared globally in the source code, the compiler of the present invention emits in the target code a declaration of a global scalar variable. It further emits in the target code a start trap. When executed, the start trap allocates memory and a data structure for the global variables involving parallelism. The start trap also initializes the data structures and global variables involving parallelism. Finally, the compiler of the present invention emits in the target code one or more statements which, at run time, will cause the start trap to be invoked before the execution of any statement in which one of the global variables involving parallelism is read from or written to.
摘要翻译： 用于编译适于与数据并行计算机一起使用的计算机程序的编译器。 编译器支持涉及并行性的变量。 涉及并行性的变量是并行变量，称为形状的并行变量的模板，以及并行变量的指针。 对于涉及在源代码中全局声明的并行性的每个变量，本发明的编译器在目标代码中发出全局标量变量的声明。 它进一步在目标代码中发出启动陷阱。 执行时，启动陷阱为涉及并行的全局变量分配内存和数据结构。 启动陷阱还初始化涉及并行性的数据结构和全局变量。 最后，本发明的编译器在目标代码中发送一个或多个语句，其在运行时将在执行任何涉及并行性的全局变量之一的语句之前调用启动陷阱， 写给
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2.发明授权System and method for compiling a source code supporting data parallel variables 失效用于编译支持数据并行变量的源代码的系统和方法
公开(公告)号：US5278986A
公开(公告)日：1994-01-11
申请号：US805566
申请日：1991-12-13
摘要： A compiler for compiling a computer program which is adapted for use with a data parallel computer. The compiler supports variables which involve parallelism. Variables which involve parallelism are parallel variables, templates for parallel variables called shapes, and pointers to parallel variables. For each variable involving parallelism declared globally in the source code, the compiler of the present invention emits in the target code a declaration of a global scalar variable. It further emits in the target code a start trap. When executed, the start trap allocates memory and a data structure for the global variables involving parallelism. The start trap also initializes the data structures and global variables involving parallelism. Finally, the compiler of the present invention emits in the target code one or more statements which, at run time, will cause the start trap to be invoked before the execution of any statement in which one of the global variables involving parallelism is read from or written to.
摘要翻译： 用于编译适于与数据并行计算机一起使用的计算机程序的编译器。 编译器支持涉及并行性的变量。 涉及并行性的变量是并行变量，称为形状的并行变量的模板，以及并行变量的指针。 对于涉及在源代码中全局声明的并行性的每个变量，本发明的编译器在目标代码中发出全局标量变量的声明。 它进一步在目标代码中发出启动陷阱。 执行时，启动陷阱为涉及并行的全局变量分配内存和数据结构。 启动陷阱还初始化涉及并行性的数据结构和全局变量。 最后，本发明的编译器在目标代码中发送一个或多个语句，其在运行时将在执行任何涉及并行性的全局变量之一的语句之前调用启动陷阱， 写给
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3.发明授权System for compiling parallel communications instructions including their embedded data transfer information 失效用于编译并行通信指令的系统，包括其嵌入式数据传输信息
公开(公告)号：US5355492A
公开(公告)日：1994-10-11
申请号：US788052
申请日：1991-11-05
申请人： James L. Frankel , Michael L. Best , Karen C. Jourdenais , Joshua E. Simons , Steven J. Sistare
发明人： James L. Frankel , Michael L. Best , Karen C. Jourdenais , Joshua E. Simons , Steven J. Sistare
摘要： The present invention is directed towards a compiler for processing parallel communication instructions on a data parallel computer. The compiler of the present invention comprises a front end, a middle end, an optimizer, and a back end. The front end constructs a parse tree which includes nodes representative of parallel communication instructions. The middle end generates an intermediate representation (IR) tree from the parse tree. The IR tree includes general parallel communication IR nodes representative of target code to carry out parallel communication with general communication. An efficient parallel communication module of the optimizer replaces general parallel communication IR nodes with grid parallel communication IR nodes where doing so would result in more efficient target code. The grid parallel communication IR nodes represent target code to carry out parallel communication instructions with grid communication. The back end generates target code from the optimized IR tree.
摘要翻译： 本发明涉及用于在数据并行计算机上处理并行通信指令的编译器。 本发明的编译器包括前端，中端，优化器和后端。 前端构造一个解析树，其中包含代表并行通信指令的节点。 中间端从解析树生成中间表示（IR）树。 IR树包括代表目标代码的通用并行通信IR节点，用于与通用通信进行并行通信。 优化器的高效的并行通信模块将通用并行通信IR节点替换并网通信IR节点，这样做将导致更有效的目标代码。 网格并行通信IR节点表示用网格通信执行并行通信指令的目标代码。 后端从优化的IR树生成目标代码。
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4.发明授权Compiler for performing incremental live variable analysis for data-parallel programs 失效用于对数据并行程序进行增量实时变量分析的编译器
公开(公告)号：US5355494A
公开(公告)日：1994-10-11
申请号：US806026
申请日：1991-12-12
摘要： A compiler for compiling a computer program wherein the computer program is adapted for use with a data parallel computer. The compiler comprises an optimizer which optimizes the compiled code. In optimizing the compiled code, the optimizer performs live variable analysis. With regard to performing live variable analysis, the optimizer of the present invention is adapted for use with data parallel languages. Additionally, the optimizer is computationally efficient at compile time. Further, the optimizer operates in an incremental manner.
摘要翻译： 一种用于编译计算机程序的编译器，其中所述计算机程序适于与数据并行计算机一起使用。 编译器包括优化编译代码的优化器。 优化编译代码时，优化器执行实时变量分析。 关于执行实时变量分析，本发明的优化器适于与数据并行语言一起使用。 另外，优化器在编译时在计算上是有效的。 此外，优化器以增量方式运行。
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公开(公告)号：US5561801A
公开(公告)日：1996-10-01
申请号：US171984
申请日：1993-12-23
申请人： Joshua E. Simons , James L. Frankel
发明人： Joshua E. Simons , James L. Frankel
IPC分类号： G06F9/45
CPC分类号： G06F8/45
摘要： A compiler for compiling a computer program wherein the computer program is adapted for use with a data parallel computer. The compiler comprises a front end which generates a parse tree from a source code. In generating the parse tree, the front end coordinates the compilation of type conversion operations and promotion operations such that run-time efficiency is maximized. In other words, the front end compiles the type conversion operations and promotion operations in an order which maximizes run-time efficiency.
摘要翻译： 一种用于编译计算机程序的编译器，其中所述计算机程序适于与数据并行计算机一起使用。 编译器包括从源代码生成解析树的前端。 在生成解析树时，前端协调类型转换操作和升级操作的编译，使运行时效率最大化。 换句话说，前端按照使运行时效率最大化的顺序编译类型转换操作和升级操作。
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公开(公告)号：US5515535A
公开(公告)日：1996-05-07
申请号：US307533
申请日：1994-09-15
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： An optimizer for optimizing an intermediate representation (IR) tree having multiple nodes. The IR tree represents a partial compilation of a source code. The source code is written using a high level language supporting data parallel processing. According to the present invention, the optimizer optimizes the IR tree by minimizing the number and size of temporary parallel variables in the IR tree. Such minimization optimizes the IR tree because temporary parallel variables require an enormous amount of space in memory.
摘要翻译： 用于优化具有多个节点的中间表示（IR）树的优化器。 IR树代表源代码的部分编译。 源代码是使用支持数据并行处理的高级语言编写的。 根据本发明，优化器通过使IR树中临时并行变量的数量和大小最小化来优化IR树。 这种最小化优化了IR树，因为临时并行变量需要大量的内存空间。
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公开(公告)号：US06741245B1
公开(公告)日：2004-05-25
申请号：US09298739
申请日：1999-04-23
IPC分类号： G06T1700
CPC分类号： G06T15/20 , A63F2300/6018 , A63H33/042 , B33Y80/00
摘要： A method for decorating a virtual world model first builds a physical model from a plurality of building blocks. Each building block includes a microcontroller coupled to a plurality of connectors. The connectros are for physically and electronically connecting the blocks in a three-dimensional structure to form the model. An arrangement of the blocks in the model is derived by connecting the model to a host computer. The arrangement is expressed as a set of logical axioms. The set of logical axioms is processed by a logic program to identify large scale structural elements of the model, and decorative attributes are assigned to the large. scale structural elements.
摘要翻译： 用于装饰虚拟世界模型的方法首先从多个构建块构建物理模型。 每个构建块包括耦合到多个连接器的微控制器。 连接器用于物理和电子连接三维结构中的块以形成模型。 通过将模型连接到主机来获得模型中的块的排列。 该安排被表达为一组逻辑公理。 一组逻辑公理由逻辑程序处理，以识别模型的大规模结构元素，并将装饰属性分配给大型。 规模结构要素。
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公开(公告)号：US06526375B1
公开(公告)日：2003-02-25
申请号：US09298235
申请日：1999-04-23
IPC分类号： G06F944
CPC分类号： H05K7/1459 , B33Y50/00 , G06F15/803 , H01R13/514
摘要： In a self-configuring store-and-forward computer network, a plurality of processors are each housed in an enclosure having a top surface and a bottom surface. Each processor has an associated block identification number. An array of m by n radially symmetric connectors are arranged on the top surface and on the bottom surface of each enclosure. Each connector has an associated connector identification number. The connectors physically and electronically couple the plurality of processors as a three-dimensional structure. Communications controller in each of the processors exchange the block and connector identification numbers between the processors and a host computer to determine an ordered list of connector numbers that is used to route messages between any of the processors and the host computer.
摘要翻译： 在自配置存储和转发计算机网络中，多个处理器分别容纳在具有顶表面和底表面的外壳中。 每个处理器具有关联的块标识号。 在每个外壳的顶表面和底表面上布置了由n个径向对称连接器组成的阵列。 每个连接器都具有相关联的连接器标识号。 所述连接器以三维结构物理和电子方式耦合所述多个处理器。 每个处理器中的通信控制器在处理器和主计算机之间交换块和连接器标识号，以确定用于在任何处理器和主计算机之间路由消息的连接器号的有序列表。
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9.发明授权公开(公告)号：US06256719B1
公开(公告)日：2001-07-03
申请号：US09298376
申请日：1999-04-23
申请人： James L. Frankel
发明人： James L. Frankel
IPC分类号： G06F1580
CPC分类号： G06F15/80 , G06F15/17343
摘要： Provided is a method for routing messages among arbitrarily connected processors. Each processor is housed in an enclosure including a top surface and a bottom surface, and an array of m by n radially symmetric connectors are arranged on the top surface and on the bottom surface of the enclosure to interconnect the processors as a rigid three-dimensional structure. An unique block identification number is associated with each processor. A unique connector identification number is associated with each connector of a particular processor. A message is generated to include an ordered list of connector identification numbers, and the message is forwarded to a destination process according to the ordered list.
摘要翻译： 提供了一种在任意连接的处理器之间路由消息的方法。 每个处理器被容纳在包括顶表面和底表面的外壳中，并且在外壳的顶表面和底表面上布置有由m个径向对称的连接器组成的阵列，以将处理器作为刚性三维 结构体。 与每个处理器相关联的唯一块标识号。 唯一的连接器标识号与特定处理器的每个连接器相关联。 生成消息以包括连接器标识号的有序列表，并且根据订购列表将消息转发到目的地进程。
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