公开(公告)号：US20180059742A1

公开(公告)日：2018-03-01

申请号：US15252501

申请日：2016-08-31

Applicant: Western Digital Technologies, Inc.

Inventor： DEAN MITCHAM JENKINS ,  ROBERT P. RYAN

IPC: G06F1/18 ,  H05K7/14 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F1/187 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4282 ,  G11B33/126 ,  G11B33/128 ,  H05K7/1459 ,  H05K7/1488

Abstract: A Data Storage Device (DSD) enclosure includes a chassis and at least one backplane mounted in the chassis. According to one aspect, each backplane includes a row of DSD slots and a switch slot located in a middle portion of the row of DSD slots. A plurality of signal traces connect the DSD slots to the switch slot.

公开(公告)号：US20170245388A1

公开(公告)日：2017-08-24

申请号：US15521616

申请日：2014-10-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Terrel L. MORRIS

IPC: H05K7/14 ,  H05K1/11 ,  H05K7/02 ,  H05K1/18

CPC classification number: H05K7/1459 ,  H01L2924/0002 ,  H05K1/117 ,  H05K1/181 ,  H05K7/023 ,  H05K7/1427 ,  H05K7/1451 ,  H05K7/1452 ,  H01L2924/00

Abstract: A network packaging system can include a circuit board that includes a chip located substantially in a center of the board. A backplane is in communication with the chip and located along on a first edge of the circuit board. A plurality of connector ports are arranged along the perimeter of at least two other edges of the circuit board. A plurality of traces connects the plurality of connector ports to the chip. A support structure houses one or more circuit boards, with at least two sidewall surfaces of the support structure extending substantially orthogonal to and coextensive with each of the at least two edges of the circuit board. The support structure includes a plurality of apertures extending through the one or more surfaces spatially aligned with each of the plurality of connector ports.

公开(公告)号：US08653377B2

公开(公告)日：2014-02-18

申请号：US13080013

申请日：2011-04-05

Applicant: Shaun L. Champion ,  Philip H. Ives ,  Harry A. Andreas ,  Norman C. Lee ,  Karrie D. Dooley

Inventor： Shaun L. Champion ,  Philip H. Ives ,  Harry A. Andreas ,  Norman C. Lee ,  Karrie D. Dooley

IPC: H05K1/00

CPC classification number: H05K7/1459

Abstract: Embodiments enable for the creation of microelectronic modules that may be configured in any order within a microelectronic assembly. The microelectronic modules provide for point-to-point interconnects between the modules using a standardized connector that is the same for each module. This, thereby, eliminates the need for a backplane. The modules may be configured in any order within a microelectronic assembly. No prior knowledge regarding the functions of an individual microelectronic module is required if the microelectronic modules conform to the standardized I/O of the standardized connector.

Abstract translation: 实施例能够创建可以在微电子组件内以任何顺序配置的微电子模块。 微电子模块使用对于每个模块相同的标准化连接器来提供模块之间的点对点互连。 因此，消除了对背板的需要。 模块可以以微电子组件内的任何顺序配置。 如果微电子模块符合标准化连接器的标准化I / O，则不需要关于单个微电子模块的功能的现有知识。

公开(公告)号：US08364878B2

公开(公告)日：2013-01-29

申请号：US13366191

申请日：2012-02-03

Applicant: Haw-Jyh Liaw ,  David Nguyen

Inventor： Haw-Jyh Liaw ,  David Nguyen

IPC: G06F13/42

CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

Abstract: A memory module includes a substrate, a plurality of signal lines, a clock line and a plurality of memory devices. The plurality of signal lines including first and second signal lines routed alongside one another where, for each of the first and second signal lines, a respective signal, starting at a corresponding first edge finger, traverses in sequence, a respective first segment of a respective signal line, a respective turn portion of the respective signal line, and a respective second segment of the respective signal line. The clock line is to provide a clock signal that traverses in sequence, a second edge finger, the first segment of the clock line, the turn portion of the clock line, and the second segment of the clock line. The respective signals traverse and the clock signal line arrive at the plurality of memory devices in sequence.

Abstract translation: 存储器模块包括衬底，多条信号线，时钟线和多个存储器件。 多条信号线包括彼此并行布置的第一和第二信号线，其中，对于第一和第二信号线中的每一条，从相应的第一边缘指状开始的相应信号依次穿过相应的第一段， 信号线，相应信号线的相应转弯部分以及相应信号线的相应第二部分。 时钟线是提供顺序穿过的时钟信号，第二边缘手指，时钟线的第一段，时钟线的转弯部分和时钟线的第二段。 相应的信号遍历并且时钟信号线依次到达多个存储器件。

公开(公告)号：US08214575B2

公开(公告)日：2012-07-03

申请号：US12975313

申请日：2010-12-21

Applicant: Haw-Jyh Liaw ,  David Nguyen

Inventor： Haw-Jyh Liaw ,  David Nguyen

IPC: G06F13/42

CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

Abstract: A memory module includes a first signal line to carry a first signal. The first signal line has (i) a first line segment disposed along a length of the memory module and coupled to a termination, and (ii) a second line segment disposed along a width of the memory module and coupled to an edge finger. The first line segment and the second line segment are coupled together at a turn. A first synchronous memory device and a second synchronous memory device are coupled to the first line segment. The first signal arrives at the first synchronous memory device and the second synchronous memory device in a sequential manner. The memory module includes a clock line routed alongside the first signal line. A clock signal arrives at the first synchronous memory device and the second synchronous memory device in sequence alongside the first signal traversing along the first signal line.

Abstract translation: 存储器模块包括用于承载第一信号的第一信号线。 第一信号线具有（i）沿着存储器模块的长度设置并耦合到终端的第一线段，以及（ii）沿着存储器模块的宽度设置并耦合到边缘指状物的第二线段。 第一线段和第二线段在转弯处耦合在一起。 第一同步存储器件和第二同步存储器件耦合到第一线段。 第一信号以顺序的方式到达第一同步存储器件和第二同步存储器件。 存储器模块包括沿着第一信号线路线路由的时钟线。 时钟信号沿着沿着第一信号线的第一信号沿着顺序到达第一同步存储器件和第二同步存储器件。

公开(公告)号：US20110286154A1

公开(公告)日：2011-11-24

申请号：US13193246

申请日：2011-07-28

Applicant: Joseph C. Coffey ,  Bradley Blichfeldt

Inventor： Joseph C. Coffey ,  Bradley Blichfeldt

IPC: H02B1/04

CPC classification number: H02H3/006 ,  H02H3/08 ,  H02H3/10 ,  H02J1/08 ,  H02J1/108 ,  H02M3/1584 ,  H05K7/1439 ,  H05K7/1457 ,  H05K7/1459 ,  Y10T307/492 ,  Y10T307/50 ,  Y10T307/653

Abstract: A modular power distribution system comprises a chassis; and a backplane including a power input, and a plurality of module connection locations. A plurality of modules are mounted in the chassis, each module mounted to one of the module connection locations. Each module includes: (i) an OR-ing diode; (ii) a circuit protection device; (iii) a microprocessor controlling the circuit protection device; and (iv) a power output connection location. A circuit option switch is located on each module for setting the current limits for each module. A control module is provided connected to the backplane.

Abstract translation: 模块化配电系统包括底盘; 以及包括电源输入和多个模块连接位置的背板。 多个模块安装在机架中，每个模块安装到模块连接位置之一。 每个模块包括：（i）OR-二极管; （ii）电路保护装置; （iii）控制电路保护装置的微处理器; 和（iv）电力输出连接位置。 电路选项开关位于每个模块上，用于设置每个模块的电流限制。 提供连接到背板的控制模块。

公开(公告)号：US20110060860A1

公开(公告)日：2011-03-10

申请号：US12991562

申请日：2008-05-07

Applicant: Mats Rimborg

Inventor： Mats Rimborg

IPC: G06F13/00

CPC classification number: H05K7/1459 ,  G06F13/409 ,  Y02D10/14 ,  Y02D10/151

Abstract: A backplane arrangement 200; 500 and method for distributing network connections in said backplane arrangement 200; 500 comprising a number of board positions Ac-Fc; Gc-Kc each arranged to operatively receive a board Ab-Fb; Gb-Kb, and a backplane-network arrangement 250, 300; 550, 600, 600′ arranged to operatively make a plurality of network connections a-n; a-g available at a first board position Ac; Gc. The backplane arrangement 200; 500 is characterized in f/?af a first allocation arrangement Aen1-Aen14; Gen8-Gen14 is arranged to operatively allocate a set of the available network connections a-n; a-g to be used by a board Ab received in the first board position Ac; Gc; and a first bypass arrangement Ap; Aps; Aps'; Gp is arranged to operatively bypass a set of the available network connections b-n; b-g unallocated at the first board position Ac; Gc to a second subsequent board position Bc; Hc via the backplane-network arrangement 250; 550.

Abstract translation: 背板装置200; 500和用于在所述背板装置200中分配网络连接的方法; 500包含多个板位置Ac-Fc; Gc-Kc各自布置成可操作地接收板Ab-Fb; Gb-Kb和背板网络布置250,300; 550,600,600'，用于可操作地使多个网络连接a-n; a-g可在第一板位置Ac; GC。 背板装置200; 500的特点是f /？af第一次分配安排Aen1-Aen14; Gen8-Gen14被布置成可操作地分配一组可用网络连接a-n; a-g被董事会使用Ab获得在第一板位置Ac; GC; 和第一旁路装置Ap; Aps; Aps' Gp被布置成可操作地绕过一组可用网络连接b-n; b-g未分配在第一板位置Ac; Gc到第二个后续的董事会职位Bc; Hc通过背板网络布置250; 550。

公开(公告)号：US07844768B2

公开(公告)日：2010-11-30

申请号：US11389021

申请日：2006-03-27

Applicant: Yoshimasa Tanaka

Inventor： Yoshimasa Tanaka

IPC: H05K7/10 ,  G06F13/00 ,  G06F15/177 ,  G06F15/00

CPC classification number: H05K7/1459 ,  H05K7/1498

Abstract: Each chassis includes a back plane having a plurality of slots and a CPU blade server and CMMs which are inserted in the slots, respectively. The back plane has a storage unit storing a housing number for identifying the housing, in-housing chassis numbers for identifying the chassis in the housing, and in-chassis slot IDs for identifying the slots. When the blade server is inserted into the corresponding slot, the blade server acquires the in-chassis slot ID from the back plane. When the CMMs are inserted into the corresponding slots, the CMMs acquire housing numbers and in-housing chassis numbers from the back plane, holds the housing number and the in-housing chassis numbers, and manages the configuration of the blade server through the back plane. One of the CMMs manages the other CMMs.

Abstract translation: 每个底盘包括分别具有多个槽的背板和插入槽中的CPU刀片服务器和CMM。 背板具有存储用于识别外壳的外壳编号的存储单元，用于识别外壳中的机箱的机箱内编号，以及用于识别时隙的机架内插槽ID。 当刀片服务器插入到相应的插槽中时，刀片服务器从背板获取机箱内插槽ID。 当CMM插入到相应的插槽中时，CMM从背板获取外壳编号和机箱底座编号，保持外壳编号和机箱底座编号，并通过后平面管理刀片服务器的配置 。 其中一个CMM管理其他CMM。

公开(公告)号：US07619886B2

公开(公告)日：2009-11-17

申请号：US10159087

申请日：2002-05-31

Applicant: Joseph Soetemans ,  Dion Pike ,  Gavin Gonsalves ,  Jonathan Spratley

Inventor： Joseph Soetemans ,  Dion Pike ,  Gavin Gonsalves ,  Jonathan Spratley

IPC: H05K7/20

CPC classification number: H05K7/1459

Abstract: The present invention comprises a method and apparatus for providing a common support services infrastructure that allows a network element shelf to be used with circuit card configurations that provide enhanced and/or new data path functionality without requiring the expensive and time consuming redesign of the entire shelf unit. In one embodiment, the invention provides support services including common control and housekeeping services to a subshelf bay into which one or more subshelves may be installed. In one embodiment, the common support services that are provided include power supply services, environmental control services, information display services, and operational control and management services. In one embodiment, the subshelf bay is provided with standardized means used to supply the common support services to the subshelves. In one embodiment, each sub-shelf contains its own midplane and is operationally independent from other subshelves. The use of subshelves and the separation of providing support services (provided by the infrastructure) from providing data path functionality (provided by the subshelves) allows data path functionality to be enhanced by replacement of a subshelf without requiring redesign of the entire shelf unit.

Abstract translation: 本发明包括一种用于提供共同的支持服务基础设施的方法和装置，其允许将网络元件架与电路卡配置一起使用，所述电路卡配置提供增强的和/或新的数据路径功能，而不需要对整个搁板进行昂贵且耗时的重新设计 单元。 在一个实施例中，本发明提供支持服务，其包括可以安装一个或多个子空间的子房架的共同控制和家政服务。 在一个实施例中，提供的公共支持服务包括供电服务，环境控制服务，信息显示服务以及操作控制和管理服务。 在一个实施例中，子台架设置有用于将共同支撑服务提供给子窗口的标准化装置。 在一个实施例中，每个子架包含其自己的中平面，并且在操作上独立于其他子架。 使用子窗口和提供支持服务（由基础设施提供）提供数据路径功能（由子窗口提供）的分离允许通过替换子机架来增强数据路径功能，而不需要重新设计整个机架单元。

公开(公告)号：US07554796B2

公开(公告)日：2009-06-30

申请号：US11654367

申请日：2007-01-17

Applicant: Joseph C. Coffey ,  Bradley Blichfeldt

Inventor： Joseph C. Coffey ,  Bradley Blichfeldt

IPC: G01F1/26 ,  H02P1/28

CPC classification number: H02H3/006 ,  H02H3/08 ,  H02H3/10 ,  H02J1/08 ,  H02J1/108 ,  H02M3/1584 ,  H05K7/1439 ,  H05K7/1457 ,  H05K7/1459 ,  Y10T307/492 ,  Y10T307/50 ,  Y10T307/653

Abstract: A modular power distribution system comprises a chassis; and a backplane including a power input, and a plurality of module connection locations. A plurality of modules are mounted in the chassis, each module mounted to one of the module connection locations. Each module includes: (i) an OR-ing diode; (ii) a circuit protection device; (iii) a microprocessor controlling the circuit protection device; and (iv) a power output connection location. A circuit option switch is located on each module for setting the current limits for each module. A control module is provided connected to the backplane.

Abstract translation: 模块化配电系统包括底盘; 以及包括电源输入和多个模块连接位置的背板。 多个模块安装在机架中，每个模块安装到模块连接位置之一。 每个模块包括：（i）OR-二极管; （ii）电路保护装置; （iii）控制电路保护装置的微处理器; 和（iv）电力输出连接位置。 电路选项开关位于每个模块上，用于设置每个模块的电流限制。 提供连接到背板的控制模块。