公开(公告)号：US06865658B2

公开(公告)日：2005-03-08

申请号：US10010796

申请日：2001-12-07

申请人： Nobuaki Tomori ,  Katsumi Fukumoto ,  Kazuhiro Okamoto

发明人： Nobuaki Tomori ,  Katsumi Fukumoto ,  Kazuhiro Okamoto

IPC分类号： G06F12/16 ,  G06F3/06 ,  G06F3/08 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0246

摘要： A data management system and method use link information stored with a plurality of data segments. The data management system includes: a nonvolatile semiconductor storage section including a plurality of blocks; a storage control section; a data management system control section for processing data to be stored in the nonvolatile semiconductor storage section; and a data management system memory section for storing management data. The data management system control section performs data management by dividing the data into data segments in units of a sector which is a logical unit for data management; storing data link information which indicates the ordinal relationship of the data segments, together with the data segments, in the nonvolatile semiconductor storage section; and storing, as link information in each sector, information about immediately-previous and immediately-subsequent data storage sites.

摘要翻译： 数据管理系统和方法使用存储有多个数据段的链接信息。 数据管理系统包括：包括多个块的非易失性半导体存储部; 存储控制部; 数据管理系统控制部分，用于处理要存储在非易失性半导体存储部分中的数据; 以及用于存储管理数据的数据管理系统存储部分。 数据管理系统控制部分通过将数据划分为数据段，以扇区为单位进行数据管理，该扇区是用于数据管理的逻辑单元; 将指示数据段的顺序关系的数据链路信息与数据段一起存储在非易失性半导体存储部分中; 并且作为每个扇区中的链接信息存储关于紧接在前和紧随其后的数据存储站点的信息。

公开(公告)号：US5146431A

公开(公告)日：1992-09-08

申请号：US585771

申请日：1990-09-20

申请人： Michael D. Eby ,  Katsumi Fukumoto ,  Michael J. Griffus ,  Giao N. Pham

发明人： Michael D. Eby ,  Katsumi Fukumoto ,  Michael J. Griffus ,  Giao N. Pham

IPC分类号： G11C17/00 ,  G11C8/04 ,  G11C14/00 ,  G11C16/02

CPC分类号： G11C8/04

摘要： In a non-volatile DRAM (NVDRAM) memory device comprised of NVDRAM cells, each comprising a DRAM cell and an EEPROM cell, a method and apparatus for the page recall of data whereby the page recall start address may be specified by the user through the memory device's external control pins. A page of memory cells is defined as all of the memory cells connected to a single word line. During any recall operation, data are recalled from EEPROM to DRAM in only one memory cell per bit line. The externally specified page recall start address is input onto an external pad. It is then transmitted through an address selector circuit into the inputs of a counter circuit. The outputs of the counter circuit serve as the page recall start address, which reenters the address selector circuitry to be transmitted to address decoding circuitry.

摘要翻译： 在由包括DRAM单元和EEPROM单元的NVDRAM单元组成的非易失性DRAM（NVDRAM）存储器件中，用于页面调用数据的方法和装置，由此可以由用户通过 存储器件的外部控制引脚。 存储单元的页面被定义为连接到单个字线的所有存储器单元。 在任何调用操作期间，每个位线只能在一个存储单元中将数据从EEPROM调用到DRAM。 外部指定的页面调用起始地址被输入到外部焊盘。 然后通过地址选择器电路传输到计数器电路的输入端。 计数器电路的输出作为寻呼开始地址，将地址选择器电路重新输入到地址解码电路。

公开(公告)号：US06000004A

公开(公告)日：1999-12-07

申请号：US884981

申请日：1997-06-30

申请人： Katsumi Fukumoto

发明人： Katsumi Fukumoto

IPC分类号： G06F12/14 ,  G06F12/02 ,  G06F12/08 ,  G06F12/16 ,  G06F21/02 ,  G06F21/24 ,  G11C16/02

CPC分类号： G06F12/0246

摘要： A nonvolatile semiconductor memory device including: a memory cell array for storing data therein in a nonvolatile manner; block protect data storage regions provided for the respective blocks, for storing data therein in a nonvolatile manner; and block protect means for disabling an erase and a write of data from/into a block, if block protect data has been stored in the block protect data storage region of the block and a write protect signal has been activated. The device is characterized by: erase complete data storage regions, provided for the respective blocks, for storing data therein in a nonvolatile manner; erase complete data set means for writing erase complete data into the erase complete data storage region of a block after an erase of data from the block has been completed; and re-erase enable means for enabling an erase of data from a block if the erase complete data has not been stored in the erase complete data storage region of the block, irrespective of a function of the block protect means.

摘要翻译： 一种非易失性半导体存储器件，包括：用于以非易失性方式存储数据的存储单元阵列; 块保护为各个块提供的数据存储区域，用于以非易失性方式存储数据; 以及块保护装置，用于如果块保护数据已经存储在块的块保护数据存储区域中并且写保护信号已经被激活，则禁止从块进入数据的擦除和写入。 该装置的特征在于：擦除为各个块提供的完整的数据存储区域，以非易失的方式存储数据; 擦除完成数据组装置，用于在从块的数据擦除完成之后将擦除完成数据写入块的擦除完成数据存储区域; 以及如果擦除完成数据尚未存储在块的擦除完成数据存储区域中，则与擦除块保护装置的功能无关地重新擦除使能装置，用于使能擦除来自块的数据。

公开(公告)号：US5619470A

公开(公告)日：1997-04-08

申请号：US459098

申请日：1995-06-02

申请人： Katsumi Fukumoto

发明人： Katsumi Fukumoto

IPC分类号： G11C11/22 ,  G11C14/00 ,  G11C7/00

CPC分类号： G11C14/00 ,  G11C11/22

摘要： A memory device including a memory for storing data having volatile and non-volatile capability; an access circuit for reading/writing the data stored in a volatile state at an address in said memory in accordance with an access command indicating the address; a transfer circuit for transferring the data stored in said memory from the volatile state into a non-volatile state; and a recall circuit for recalling the data stored in said memory in the non-volatile state into the volatile state, wherein said recall circuit selectively performs a recall operation for a section of said memory which includes the address before said access circuit performs a read/write operation for the data when the data at the address is stored in the non-volatile state.

摘要翻译： 一种存储器件，包括用于存储具有挥发性和非易失性能力的数据的存储器; 访问电路，用于根据指示地址的访问命令读取/写入存储在所述存储器中的地址处的易失性状态的数据; 用于将存储在所述存储器中的数据从所述易失性状态转移到非易失性状态的传送电路; 以及用于将在非易失性状态下存储在所述存储器中的数据调回到易失性状态的调用电路，其中所述调用电路选择性地对所述存储器的一部分进行调用操作，所述存储器包括所述存取电路在所述存取电路执行读/ 当地址中的数据存储在非易失性状态时，对数据进行写操作。

公开(公告)号：US5381379A

公开(公告)日：1995-01-10

申请号：US163180

申请日：1993-12-03

申请人： Katsumi Fukumoto

发明人： Katsumi Fukumoto

IPC分类号： G11C7/00 ,  G11C11/22 ,  G11C14/00 ,  G11C8/00

CPC分类号： G11C11/22 ,  G11C14/00 ,  G11C7/00

摘要： An NVDRAM memory device which performs a recall operation in which non-volatile data stored in memory cell is converted to volatile data in a recall mode, a store operation in which the volatile data stored in the memory cell is converted to the non-volatile data in a store mode, and a read/write operation in which the volatile data stored in the memory cell is read or written in a DRAM mode, includes: a counter circuit for counting the number of the recall or store operations, which generates an inhibit signal in the case where a counted value exceeds a predetermined value and resets the counted value in response to an external reset signal; and an inhibit unit for inhibiting the recall or store operation in response to the inhibit signal given from the counter circuit.

摘要翻译： 一种NVDRAM存储器件，其执行调用操作，其中存储在存储器单元中的非易失性数据在调用模式中被转换成易失性数据;存储操作，其中将存储在存储单元中的易失性数据转换为非易失性数据 在存储模式中，存储单元中的易失性数据以DRAM模式被读取或写入的读/写操作包括：计数器，用于对召回或存储操作的次数进行计数，产生抑制 在计数值超过预定值的情况下响应于外部复位信号复位计数值的信号; 以及禁止单元，用于响应于从计数器电路给出的禁止信号来禁止调用或存储操作。

公开(公告)号：US4941863A

公开(公告)日：1990-07-17

申请号：US329936

申请日：1989-03-28

申请人： Keiichi Sampei ,  Masami Kawasaki ,  Yosihito Dei ,  Katsumi Fukumoto ,  Kazuo Furukawa

发明人： Keiichi Sampei ,  Masami Kawasaki ,  Yosihito Dei ,  Katsumi Fukumoto ,  Kazuo Furukawa

IPC分类号： F16H9/14

CPC分类号： F16H9/14

摘要： A stepless speed change mechanism in a belt transmission device comprising a first belt passed through a groove in a drive pulley and a first groove in an intermediate pulley, and a second belt passed through a second groove in the intermediate pulley and a groove in a driven pulley for transmitting rotation from the drive pulley to the driven pulley via the intermediate pulley. The first groove and the second groove of the intermediate pulley have an axial width gradually decreasing radially inwardly of the pulley. A partition provided between and defining the first and second grooves of the intermediate pulley is movable axially of the pulley to thereby vary the pitch diameter of each of the first and second grooves and steplessly change the speed of rotation to be transmitted from the drive pulley to the driven pulley. The state of contact of the first belt with the first groove portion is adjusted to be different from the state of contact of the second belt with the second groove portion so that when the partition moves axially for the speed change, the axial component of the pushing force exerted on the partition by one of the first and second belts differs in magnitude from the axial component of the reaction force exerted on the partition by the other belt.

摘要翻译： 一种带式传动装置中的无级变速机构，包括通过驱动带轮中的槽的第一带和中间带轮中的第一槽，以及穿过中间带轮中的第二槽的第二带和驱动的槽 滑轮，用于经由中间滑轮将来自驱动滑轮的旋转传递到从动滑轮。 中间皮带轮的第一凹槽和第二凹槽具有沿滑轮径向向内逐渐减小的轴向宽度。 设置在中间皮带轮之间并限定中间皮带轮的第一和第二凹槽之间的隔板可以在滑轮的轴向上移动，从而改变每个第一和第二凹槽的节圆直径，并且无级地改变要从驱动皮带轮传递的旋转速度 从动皮带轮。 第一带与第一槽部的接触状态被调节为不同于第二带与第二槽部的接触状态，使得当分隔件轴向移动用于变速时，推动轴向分量 由第一和第二带中的一个施加在隔板上的力的大小与通过另一带施加在隔板上的反作用力的轴向分量不同。

公开(公告)号：US06370058B1

公开(公告)日：2002-04-09

申请号：US09656314

申请日：2000-09-06

申请人： Katsumi Fukumoto

发明人： Katsumi Fukumoto

IPC分类号： G11C1400

CPC分类号： G11C14/00

摘要： A non-volatile semiconductor memory device includes a memory cell array capable of storing data in volatile and non-volatile states, and a determination circuit for determining whether a row address in a current cycle is the same as that in a previous cycle. When the row address in the current cycle is different from that in the previous cycle, a store operation is performed, where volatile data is stored in the memory cell as non-volatile data; thereafter a recall operation is performed where non-volatile data stored in the memory cell is transformed into volatile data; the resulting volatile data is stored in the memory cell and a sense amplifier, or at least one of the sense amplifier and a latch circuit. When the row address in the current cycle is the same as that in the previous cycle, a read or write operation is performed with respect to volatile data stored in the memory cell, the sense amplifier or latch circuit, but non-volatile data is not read from or written to the memory cell.

摘要翻译： 非挥发性半导体存储器件包括能够以易失性和非易失性状态存储数据的存储单元阵列，以及用于确定当前周期中的行地址是否与前一周期中的行地址相同的确定电路。 当当前周期中的行地址与前一周期中的行地址不同时，执行存储操作，其中易失性数据作为非易失性数据存储在存储单元中; 此后，存储在存储单元中的非易失性数据被变换为易失性数据，执行召回操作; 所得到的易失性数据被存储在存储单元和读出放大器中，或至少一个读出放大器和锁存电路。 当当前周期中的行地址与上一个周期中的行地址相同时，对于存储在存储单元，读出放大器或锁存电路中的易失性数据执行读或写操作，但非易失性数据不是 从存储单元读取或写入存储单元。

公开(公告)号：US5673222A

公开(公告)日：1997-09-30

申请号：US666979

申请日：1996-06-20

申请人： Katsumi Fukumoto ,  Masamitsu Taki

发明人： Katsumi Fukumoto ,  Masamitsu Taki

IPC分类号： G06F12/14 ,  G06F21/24 ,  G11C16/02 ,  G11C16/22 ,  G11C17/00 ,  G11C11/34

CPC分类号： G11C16/22

摘要： An electrically erasable and rewritable semiconductor memory device including at least one memory block, comprising: a WP signal generator for generating a WP signal for controlling protection of data stored in the memory block; a protect state setting section for setting a protect state for the memory block, the data stored in the memory block being protectable from erase/write operations when the protect state is set to the memory block; and a data protecting section for prohibiting the erase/write operations for the memory block to which the protect state is set, in the case where the WP signal is active. The WP signal generator includes: a WP set command identifying section for receiving a WP set command represented by at least one predetermined value selected from values of data and values of at least one address which are input in at least one bus cycle, and for identifying the WP set command by detecting the at least one predetermined value; and a generating section for activating the WP signal when the WP set command is identified during the WP signal is inactive.

摘要翻译： 一种电可擦除和可重写的半导体存储器件，包括至少一个存储器块，包括：WP信号发生器，用于产生用于控制对存储在存储器块中的数据的保护的WP信号; 用于设置存储块的保护状态的保护状态设置部分，当保护状态被设置到存储器块时，存储器块中存储的数据可以被保护以免擦除/写入操作; 以及数据保护部分，用于在WP信号有效的情况下禁止设置有保护状态的存储器块的擦除/写入操作。 WP信号发生器包括：WP集合命令识别部分，用于接收由至少一个预定值表示的WP设置命令，所述至少一个预定值是从在至少一个总线周期中输入的至少一个地址的数据值和值中选出的，并用于识别 通过检测所述至少一个预定值来确定所述WP设置命令; 以及当在WP信号期间识别出WP设置命令不活动时，用于激活WP信号的生成部分。

公开(公告)号：US5287319A

公开(公告)日：1994-02-15

申请号：US704425

申请日：1991-05-23

申请人： Katsumi Fukumoto

发明人： Katsumi Fukumoto

IPC分类号： G11C11/406 ,  G11C14/00 ,  G11C16/02 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C14/00 ,  G11C11/406

摘要： In the normal selfrefresh mode, the timer output selection circuit selects the timer output of a longer cycle from the timer outputs generated by the internal timer circuit, and the selected timer output supplied as an operation activation signal for the selfrefresh operation. Using this long timer output, the selfrefresh operation of DRAM cells in the memory device is performed with a low operating current which allows the memory device to be backed up by a battery. When the selfrefresh mode is set before the store operation, the timer output of a short cycle is selected from the timer outputs generated by the internal timer circuit, and the short timer output is supplied as an operation activation signal for the selfrefresh operation. Using this short timer output, the selfrefresh operation of the volatile memory means is performed. Therefore, a drop in the potential of the volatile memory portions caused by a leakage current can be quickly compensated, thus ensuring that data can be correctly stored in the volatile memory means. In the selfrecall operation mode, the timer output of an medium cycle is selected from the timer outputs generated by the internal timer circuit, and the medium timer output is supplied as an operation activation signal for the selfcall operation. Since the selfrecall operation is performed using the medium timer output, the selfrecall operation is performed at a faster speed than the normal selfrefresh operation.

摘要翻译： 在正常的自刷新模式中，定时器输出选择电路从内部定时器电路产生的定时器输出中选择较长周期的定时器输出，并且所选择的定时器输出作为自刷新操作的操作激活信号提供。 使用该长定时器输出，存储器件中的DRAM单元的自刷新操作以低操作电流执行，这允许存储器件由电池备份。 当在存储操作之前设置自刷新模式时，从内部定时器电路产生的定时器输出中选择短周期的定时器输出，并且提供短定时器输出作为自刷新操作的操作激活信号。 使用该短定时器输出，执行易失性存储装置的自刷新操作。 因此，可以快速地补偿由漏电流引起的易失性存储器部分的电位下降，从而确保数据能够被正确地存储在易失性存储装置中。 在自重操作模式中，从内部定时器电路产生的定时器输出中选择中间周期的定时器输出，并且作为自动呼叫操作的操作激活信号提供中间定时器输出。 由于使用介质定时器输出执行自重操作，所以以比正常的自刷新操作更快的速度执行自重操作。

公开(公告)号：US4934989A

公开(公告)日：1990-06-19

申请号：US329522

申请日：1989-03-28

申请人： Kazuo Furukawa ,  Keiichi Sampei ,  Yoshihiro Kato ,  Yosihito Dei ,  Katsumi Fukumoto

发明人： Kazuo Furukawa ,  Keiichi Sampei ,  Yoshihiro Kato ,  Yosihito Dei ,  Katsumi Fukumoto

IPC分类号： F16H7/08 ,  F16H7/12

CPC分类号： F16H7/1281 ,  F16H2007/0874 ,  F16H2009/166

摘要： A belt transmission in which a transmission belt is reeved around each of a reversible drive pulley and a driven pulley and which includes a pair of tension pulleys provided respectively on the taut side and the slack side of the belt in contact therewith. The two tension pulleys are biased by an elastic body to tension the belt. A first link is connected to one of the tension pulleys, and a second link to the other tension pulley. The two links are each pivotally movable in a direction for the corresponding tension pulley to tension the belt and in a direction for the tension pulley to relieve the tension. The two links are pivotally movable about a common axis. When the direction of rotation of the drive pulley is changed, reversing the taut side and the slack side of the belt, the tension imparted to the belt by the tension pulleys is automatically adjusted properly by the pivotal movement of the two links.

摘要翻译： 一种传动带，其中传动带围绕可逆驱动滑轮和从动皮带轮的每一个旋转，并且包括分别设置在与其接触的皮带的拉紧侧和松弛侧的一对张力皮带轮。 两个张力滑轮由弹性体偏压以张紧皮带。 第一连杆连接到一个张力滑轮，以及第二连杆连接到另一张力滑轮。 两个连杆都可以在相应的张力滑轮的方向上枢轴运动，以张紧皮带，并在张力滑轮的方向上缓解张力。 两个连杆可绕公共轴线枢转运动。 当驱动皮带轮的旋转方向改变时，使皮带的拉紧侧和松弛侧反转，由张力滑轮赋予皮带的张力通过两个连杆的枢转运动被适当地自动调节。