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公开(公告)号：US5786607A
公开(公告)日：1998-07-28
申请号：US654962
申请日：1996-05-29
IPC分类号： H01L27/148 , H01L29/768
CPC分类号： H01L27/14812 , H01L27/14825
摘要： A solid-state image pick-up device having a structure in which the amount of transferred charges is not reduced in a vertical CCD portion even if a pixel portion is made finer, and a method for manufacturing the solid-state image pick-up device are provided. A first p-type well and a second p-type well are formed on an N (100) silicon substrate. A vertical CCD n.sup.+ layer is formed in the second p-type well 3. Then, impurity ions are implanted into a surface layer of the N (100) silicon substrate including an upper layer portion of the vertical CCD n.sup.+ layer to form a p.sup.- layer. An isolating portion for isolating photodiode portions from the vertical CCD n.sup.+ layer and a read control portion for controlling the read of charges from the photodiode n layer are simultaneously formed on a portion adjacent to the vertical CCD n.sup.+ layer.
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公开(公告)号：US6046069A
公开(公告)日：2000-04-04
申请号：US796887
申请日：1997-02-05
IPC分类号： H01L27/148 , H01L21/00 , H01L21/339
CPC分类号： H01L27/14812 , H01L27/14825
摘要： A solid-state image pick-up device having a structure in which the amount of transferred charges is not reduced in a vertical CCD portion even if a pixel portion is made finer, and a method for manufacturing the solid-state image pick-up device are provided. A first p-type well and a second p-type well are formed on an N (100) silicon substrate. A vertical CCD n.sup.+ layer is formed in the second p-type well 3. Then, impurity ions are implanted into a surface layer of the N (100) silicon substrate including an upper layer portion of the vertical CCD n.sup.+ layer to form a p.sup.- layer. An isolating portion for isolating photodiode portions from the vertical CCD n.sup.+ layer and a read control portion for controlling the read of charges from the photodiode n layer are simultaneously formed on a portion adjacent to the vertical CCD n.sup.+ layer.
摘要翻译： 具有如下结构的固体摄像装置，即使像素部分变得更细，在垂直CCD部分中转印电荷量也不会减少的结构，以及制造固态图像拾取装置的方法 被提供。 在N（100）硅衬底上形成第一p型阱和第二p型阱。 在第二p型阱3中形成垂直CCD n +层。然后，将杂质离子注入到包括垂直CCD n +层的上层部分的N（100）硅衬底的表面层中， 层。 与垂直CCD n +层隔离光电二极管部分的隔离部分和用于控制从光电二极管n层读取电荷的读取控制部分同时形成在与垂直CCD n +层相邻的部分上。
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公开(公告)号：US20050247935A1
公开(公告)日：2005-11-10
申请号：US11122429
申请日：2005-05-05
申请人： Keishi Tachikawa
发明人： Keishi Tachikawa
IPC分类号： H01L27/148 , H01L27/146 , H01L29/04 , H04N5/335 , H04N5/341 , H04N5/355 , H04N5/357 , H04N5/369 , H04N5/372
CPC分类号： H01L27/14812 , H01L27/14656
摘要： A vertical transfer charge-coupled device for vertically transferring signal charges, a horizontal transfer charge-coupled device for receiving and horizontally transferring the transferred signal charges, an unwanted electron eliminator, and a potential barrier between the horizontal transfer charge-coupled device and the unwanted electron eliminator are provided on a semiconductor substrate. The potential barrier includes a first n-type diffusion layer, a second n-type diffusion layer that is in contact with one end thereof, and a third n-type diffusion layer that is in contact with the other end. The second n-type diffusion layer and the third n-type diffusion layer have higher impurity concentrations than the first n-type diffusion layer. As a result, a solid-state imaging device is provided with which the ability of the unwanted electron eliminator to eliminate unwanted electrons is enhanced, without decreasing the size of the charge handled by the horizontal transfer charge-coupled device, allowing image output even with a large optical volume signal.
摘要翻译： 用于垂直传送信号电荷的垂直传输电荷耦合器件，用于接收和水平传送传送的信号电荷的水平传输电荷耦合器件，不需要的电子消除器和水平传输电荷耦合器件与不需要的器件之间的势垒 电子消除器设置在半导体衬底上。 势垒包括第一n型扩散层，与其一端接触的第二n型扩散层和与另一端接触的第三n型扩散层。 第二n型扩散层和第三n型扩散层的杂质浓度比第一n型扩散层高。 结果，提供了固态成像装置，其中不需要的电子消除器消除不需要的电子的能力得到增强，而不会减小由水平传输电荷耦合器件处理的电荷的尺寸，从而允许甚至在 一个大的光量信号。
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公开(公告)号：US20070210346A1
公开(公告)日：2007-09-13
申请号：US11714191
申请日：2007-03-06
申请人： Keishi Tachikawa
发明人： Keishi Tachikawa
IPC分类号： H01L29/768
CPC分类号： H01L29/76816 , H01L27/14806
摘要： A gate electrode region of a junction transistor in a signal charge-voltage converter is allowed to have a structure that a gentle potential gradient is formed without generation of a potential barrier. Thus, it is possible to readily realize a signal charge-voltage converter which is high in S/N ratio without generation of reset noise and is excellent in signal charge-voltage conversion efficiency.
摘要翻译： 信号电荷 - 电压转换器中的结晶体管的栅电极区域被允许具有形成平缓的电位梯度而不产生势垒的结构。 因此，可以容易地实现S / N比高的信号电荷电压转换器，而不产生复位噪声，并且信号电荷 - 电压转换效率优异。
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公开(公告)号：US07259394B2
公开(公告)日：2007-08-21
申请号：US11122429
申请日：2005-05-05
申请人： Keishi Tachikawa
发明人： Keishi Tachikawa
IPC分类号： H01L29/04
CPC分类号： H01L27/14812 , H01L27/14656
摘要： A vertical transfer charge-coupled device for vertically transferring signal charges, a horizontal transfer charge-coupled device for receiving and horizontally transferring the transferred signal charges, an unwanted electron eliminator, and a potential barrier between the horizontal transfer charge-coupled device and the unwanted electron eliminator are provided on a semiconductor substrate. The potential barrier includes a first n-type diffusion layer, a second n-type diffusion layer that is in contact with one end thereof, and a third n-type diffusion layer that is in contact with the other end. The second n-type diffusion layer and the third n-type diffusion layer have higher impurity concentrations than the first n-type diffusion layer. As a result, a solid-state imaging device is provided with which the ability of the unwanted electron eliminator to eliminate unwanted electrons is enhanced, without decreasing the size of the charge handled by the horizontal transfer charge-coupled device, allowing image output even with a large optical volume signal.
摘要翻译： 用于垂直传送信号电荷的垂直传输电荷耦合器件，用于接收和水平传送传送的信号电荷的水平传输电荷耦合器件，不需要的电子消除器和水平传输电荷耦合器件与不需要的器件之间的势垒 电子消除器设置在半导体衬底上。 势垒包括第一n型扩散层，与其一端接触的第二n型扩散层和与另一端接触的第三n型扩散层。 第二n型扩散层和第三n型扩散层的杂质浓度比第一n型扩散层高。 结果，提供了固态成像装置，其中不需要的电子消除器消除不需要的电子的能力得到增强，而不会减小由水平传输电荷耦合器件处理的电荷的尺寸，从而允许甚至在 一个大的光量信号。
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公开(公告)号：US20090039395A1
公开(公告)日：2009-02-12
申请号：US12185314
申请日：2008-08-04
申请人： Keishi Tachikawa
发明人： Keishi Tachikawa
IPC分类号： H01L27/148
CPC分类号： H01L27/14812
摘要： Forming an impurity region 6 and an impurity region 5 having a lower concentration than the impurity region 6 in a lower layer region of a gate electrode close to the boundary with a signal electron-voltage conversion section of a horizontal CCD outlet makes it possible to smooth a potential distribution at the time of transfer, improve the transfer efficiency, increase the number of saturated electrons and reduce variations in the transfer efficiency and variations in saturation.
摘要翻译： 在与水平CCD出口的信号电子电压转换部分接近边界的栅电极的下层区域中形成杂质区域6和浓度低于杂质区域6的杂质区域5，可以平滑 转移时的电位分布，提高转移效率，增加饱和电子数，减少转移效率和饱和度变化。
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公开(公告)号：US07732843B2
公开(公告)日：2010-06-08
申请号：US12185314
申请日：2008-08-04
申请人： Keishi Tachikawa
发明人： Keishi Tachikawa
IPC分类号： H01L31/062
CPC分类号： H01L27/14812
摘要： Forming an impurity region 6 and an impurity region 5 having a lower concentration than the impurity region 6 in a lower layer region of a gate electrode close to the boundary with a signal electron-voltage conversion section of a horizontal CCD outlet makes it possible to smooth a potential distribution at the time of transfer, improve the transfer efficiency, increase the number of saturated electrons and reduce variations in the transfer efficiency and variations in saturation.
摘要翻译： 在与水平CCD出口的信号电子电压转换部分接近边界的栅电极的下层区域中形成杂质区域6和浓度低于杂质区域6的杂质区域5，可以平滑 转移时的电位分布，提高转移效率，增加饱和电子数，减少转移效率和饱和度变化。
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