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公开(公告)号：US5809084A
公开(公告)日：1998-09-15
申请号：US691046
申请日：1996-08-01
申请人： Kazuo Shida , Mitsuru Uesugi
发明人： Kazuo Shida , Mitsuru Uesugi
CPC分类号： H04L27/2271
摘要： A data receiving system has a radio frequency unit for demodulating a series of signals transmitted at a carrier wave frequency, a local oscillating unit for generating a demodulating frequency used for the demodulation of the series of signals, an equalizing unit for removing a distortion of the series of signals demodulated in the radio frequency unit, a phase shift estimating unit for taking out phase information from the series of signals, calculating a time changing rate of the phase information and estimating a phase shift caused by a difference between the carrier wave frequency and the demodulating frequency according to the time changing rate, and a correcting unit for correcting the series of signals transmitted from the equalizing unit according to the phase shift to remove the phase shift from the series of signals. Accordingly, because the phase shift is estimated by using the phase information placed in the series of signals, an influence of a bit pattern of a series of training bits arranged in the series of signals can be removed.
摘要翻译： 数据接收系统具有用于解调以载波频率发送的一系列信号的射频单元，用于产生用于解调一系列信号的解调频率的本地振荡单元，用于消除一系列信号的失真的均衡单元 在射频单元中解调的一系列信号，相移估计单元，用于从一系列信号中取出相位信息，计算相位信息的时间变化率，并估计由载波频率和 根据时变速率的解调频率，以及校正单元，用于根据相移校正从均衡单元发送的一系列信号，以从该系列信号中去除相移。 因此，由于通过使用放置在一系列信号中的相位信息来估计相移，所以可以消除布置在一系列信号中的一系列训练位的位模式的影响。
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公开(公告)号：US5968201A
公开(公告)日：1999-10-19
申请号：US834838
申请日：1997-04-10
申请人： Kazuo Shida , Mitsuru Uesugi
发明人： Kazuo Shida , Mitsuru Uesugi
CPC分类号： H03M13/2927 , H03M13/00 , H03M13/23 , H03M13/29 , H03M13/41
摘要： Received data representing voice information is subjected to Viterbi decoding to correct an error in the received data. Thereby, the received data is decoded into second data. A path metric is calculated to determine the second data during the Viterbi decoding. A decision is made as to whether or not at least one error is present in the second data by referring to a cyclic redundancy check code in the second data. The second data is discarded when it is decided that at least one error is present in the second data. A decision is made as to whether or not the calculated path metric exceeds a threshold value. The second data is discarded when it is decided that the path metric exceeds the threshold value. The second data is converted into sound when it is decided that at least one error is not present in the second data and that the path metric does not exceed the threshold value.
摘要翻译： 代表语音信息的接收数据进行维特比解码以校正接收到的数据中的错误。 由此，接收的数据被解码为第二数据。 计算路径度量以在维特比解码期间确定第二数据。 通过参考第二数据中的循环冗余校验码来决定第二数据中是否存在至少一个错误。 当确定在第二数据中存在至少一个错误时，丢弃第二数据。 作出关于所计算的路径度量是否超过阈值的决定。 当确定路径度量超过阈值时，第二数据被丢弃。 当确定在第二数据中不存在至少一个错误并且路径度量不超过阈值时，第二数据被转换成声音。
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公开(公告)号：US6075827A
公开(公告)日：2000-06-13
申请号：US944510
申请日：1997-10-06
申请人： Kazuo Shida , Katsuhiko Hiramatsu
发明人： Kazuo Shida , Katsuhiko Hiramatsu
CPC分类号： H04L27/2071
摘要： A DQPSK mapping circuit is disclosed which comprises: a parallel decoding circuit having inputs for decoding first to 2Nth bits of input data and one symbol period prior I and Q data which are prior by one symbol period from the present decoding cycle thereof through the inputs and outputting serial first to Nth I and Q data of the present decoding period in parallel, N is a natural number; and a FF circuit for supplying the Nth I and Q data to the inputs as the one symbol period prior I and Q data in the succeeding decoding cycle of the parallel decoding circuit. The parallel decoding circuit may comprise first to Nth decoders, an Mth decoder out of the first to Nth decoders decoding 2Mth bit and (2M-1)th bits of the input data and outputs of (M-1)th decoder, M being a natural number and M.ltoreq.N, wherein the first decoder decodes the one symbol period prior I and Q data and the first and second bits of the input data.
摘要翻译： 公开了一种DQPSK映射电路，其包括：并行解码电路，其具有用于解码输入数据的第一至第2N位和从其当前解码周期通过输入之前一个符号周期的一个符号周期之前的I和Q个数据的输入，以及 并行地输出当前解码周期的第一到第N I和Q数据，N是自然数; 以及FF电路，用于将Nth I和Q数据作为并行解码电路的后续解码周期中的I和Q数据之前的一个符号周期提供给输入。 并行解码电路可以包括第一至第N解码器，第一至第N解码器中的第M个解码器解码输入数据的第2M位和第（2M-1）位，第（M-1）个解码器的输出为M 自然数和M
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