公开(公告)号：US20180351581A1

公开(公告)日：2018-12-06

申请号：US15813930

申请日：2017-11-15

申请人： Tsofun Algorithm Ltd.

发明人： Noam PRESMAN

IPC分类号： H03M13/29 ,  H03M13/31 ,  H04L1/00

CPC分类号： H03M13/2927 ,  H03M13/13 ,  H03M13/31 ,  H03M13/3746 ,  H04L1/0042 ,  H04L1/0045 ,  H04L1/0051 ,  H04L1/0057 ,  H04L1/0061

摘要： A device system and method is provided for early termination of a decoding process performed at a receiving user device. A user-specific message may be received, from a communication channel shared by multiple user devices. The user-specific message may include an error correction codeword generated by shifting an original codeword by an offset codeword uniquely associated with a target user device. The error correction codeword may be shifted based on an offset codeword uniquely associated with the receiving user device. The received message may begin to be decoded. If the receiving device is the target device, the offsets respectively associated therewith are equal and cancel, and the original message is decoded to completion. If, however, the receiving device is not the target device, the offsets respectively associated therewith are not equal and combine to form an above threshold decoding error and decoding is terminated before completion.

公开(公告)号：US20180278273A1

公开(公告)日：2018-09-27

申请号：US15702204

申请日：2017-09-12

申请人： Toshiba Memory Corporation

发明人： Naoko KIFUNE ,  Hironori UCHIKAWA ,  Daiki WATANABE

IPC分类号： H03M13/29 ,  H03M13/07 ,  H03M13/11 ,  G06F11/10 ,  G11C29/52

CPC分类号： H03M13/2927 ,  G06F11/1012 ,  G06F11/1068 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  H03M13/07 ,  H03M13/1108 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2909 ,  H03M13/2948

摘要： According to one embodiment, a decoding device that decodes a multi-dimensional error correction code having two or more component codes includes a storage unit that stores therein the multi-dimensional error correction code, an additional-information storage unit that manages each syndrome of the at least two component codes or a reliability flag indicating whether the syndrome has a value of 0 or other than 0, a decoder that performs a first decoding process in a unit of component code with respect to the multi-dimensional error correction code stored in the storage unit to detect an error vector of each component code, and a detection unit that determines whether detection of the error vector by the decoder is false detection, based on the syndrome or the reliability flag stored in the additional-information storage unit.

公开(公告)号：US20180267851A1

公开(公告)日：2018-09-20

申请号：US15461672

申请日：2017-03-17

申请人： Micron Technology, Inc.

发明人： Mustafa N. Kaynak ,  Patrick R. Khayat ,  Sivagnanam Parthasarathy

IPC分类号： G06F11/10 ,  H03M13/15 ,  H03M13/00 ,  H03M13/11

CPC分类号： G06F11/1044 ,  G06F11/1012 ,  H03M13/1125 ,  H03M13/152 ,  H03M13/2912 ,  H03M13/2927 ,  H03M13/2948 ,  H03M13/3715 ,  H03M13/6566

摘要： Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include performing a first error code correction (ECC) operation on a portion of data, performing a second ECC operation on the portion of data in response to the first ECC operation failing, and performing a third ECC operation on the portion of data in response to the second ECC operation failing.

公开(公告)号：US10057009B2

公开(公告)日：2018-08-21

申请号：US15398361

申请日：2017-01-04

申请人： LG ELECTRONICS INC.

发明人： Hyoung Gon Lee ,  In Hwan Choi ,  Byoung Gill Kim ,  Won Gyu Song ,  Jong Moon Kim ,  Jin Woo Kim

IPC分类号： H04L1/00

CPC分类号： H04L1/0041 ,  H03M13/09 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/23 ,  H03M13/2732 ,  H03M13/2909 ,  H03M13/2915 ,  H03M13/2918 ,  H03M13/2927 ,  H03M13/293 ,  H03M13/2933 ,  H03M13/356 ,  H03M13/3723 ,  H04L1/0071 ,  H04N21/235 ,  H04N21/2383 ,  H04N21/435 ,  H04N21/4382

摘要： A method of processing broadcast data in a broadcast transmitting system, the method includes randomizing, by a hardware processor, the broadcast data; first encoding, by the hardware processor, the randomized broadcast data to add first parity data for first forward error correction; second encoding, by the hardware processor, the first-encoded broadcast data to add second parity data for second forward error correction; permuting the second-encoded broadcast data; block interleaving, by the hardware processor, the permuted broadcast data; third encoding signaling information for signaling the broadcast data to add parity data; fourth encoding the third-encoded signaling information at a code rate; block interleaving the fourth-encoded signaling information; modulating the block-interleaved broadcast data and the block-interleaved signaling information; and transmitting a broadcast signal including the modulated broadcast data and the modulated signaling information.

公开(公告)号：US09935658B2

公开(公告)日：2018-04-03

申请号：US15493424

申请日：2017-04-21

申请人： Renesas Electronics Corporation

发明人： Yukitoshi Tsuboi ,  Hideo Nagano

IPC分类号： H03M13/00 ,  H03M13/29 ,  G06F11/10 ,  H03M13/11

CPC分类号： H03M13/2927 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1052 ,  H03M13/095 ,  H03M13/11 ,  H03M13/13 ,  H03M13/1575 ,  H03M13/19 ,  H03M13/29 ,  H03M13/3715 ,  H03M13/6575

摘要： A data processing apparatus includes a memory, a processor which outputs write data when making a write request to the memory, and which inputs read data when making a read request to the memory, a first circuit which is coupled between the memory and the processor, and which includes a parity generating circuit generating a parity comprising a plurality of parity bits from the write data, the parity being written with the write data into the memory, and a second circuit which is coupled between the memory and the processor, and which includes a parity check circuit detecting a presence or an absence of an error of one-bit or two-bits in the read data and the parity read from the memory.

公开(公告)号：US20180091172A1

公开(公告)日：2018-03-29

申请号：US15817535

申请日：2017-11-20

申请人： WESTERN DIGITAL TECHNOLOGIES, INC.

发明人： ISHAI ILANI ,  IDAN ALROD ,  ERAN SHARON ,  MAI GHALY

IPC分类号： H03M13/29 ,  H03M13/37 ,  H03M13/15 ,  G06F11/10 ,  G06F3/06

CPC分类号： H03M13/2927 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0689 ,  G06F11/1012 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/108 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2909 ,  H03M13/2957 ,  H03M13/3707 ,  H03M13/373 ,  H03M13/3761

摘要： A device includes a memory and a controller coupled to the memory. The controller is configured to read a codeword from a physical location of the memory. The controller is configured to write an inverse bit string to the physical location of the memory, the inverse bit string based on the codeword. The controller is configured to read a representation of the inverse bit string from the physical location of the memory. The controller is further configured to designate one or more bits of the codeword as one or more erased bits based on the codeword and the representation of the inverse bit string.

公开(公告)号：US20180048332A1

公开(公告)日：2018-02-15

申请号：US15460160

申请日：2017-03-15

申请人： SK Hynix Inc.

发明人： Naveen Kumar ,  Aman Bhatia ,  Yi-Min Lin ,  Fan Zhang

IPC分类号： H03M13/29 ,  G11C29/52 ,  H03M13/00 ,  G06F11/10

CPC分类号： H03M13/2927 ,  G06F11/1068 ,  G11C29/52 ,  H03M13/1105 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2942 ,  H03M13/2957 ,  H03M13/3707 ,  H03M13/3746 ,  H03M13/453 ,  H03M13/6502

摘要： Techniques for reducing the latency for decoding product codewords with minimal hardware architecture changes are described. In an example, a system accesses and decodes a generalized product code (GPC) codeword by using at least one of a plurality of Chase decoding procedures available on the system. A first Chase decoding procedure is configured according to first values for a set of decoding parameters. A second Chase decoding procedure is configured according to second values for the set of decoding parameters. The second values are different from the first values. The first Chase decoding procedure has a smaller latency and a higher bit error rate (BER) relative to the second Chase decoding procedure based on the first values and the second values for the set of decoding parameters.

公开(公告)号：US20170331500A1

公开(公告)日：2017-11-16

申请号：US15668565

申请日：2017-08-03

申请人： SK Hynix Inc.

发明人： Aman Bhatia ,  Yi-Min Lin ,  Naveen Kumar ,  Johnson Yen

IPC分类号： H03M13/29 ,  H03M13/37 ,  H03M13/39

CPC分类号： H03M13/2909 ,  H03M13/152 ,  H03M13/2927 ,  H03M13/2942 ,  H03M13/3746 ,  H03M13/3977

摘要： A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, and each data block having a number of data bits. The decoding apparatus is configured to decode, in parallel, a first codeword with one or more other codewords to determine error information associated with each codeword. For errors in a common data block shared between two codewords being decoded in parallel, the error information includes a data block identifier and associated error bit patterns. Further, the decoding apparatus is configured to update the codewords based on the error information.

公开(公告)号：US20170331499A1

公开(公告)日：2017-11-16

申请号：US15594830

申请日：2017-05-15

申请人： HYPERSTONE GMBH

发明人： JUERGEN FREUDENBERGER ,  JENS SPINNER ,  CHRISTOPH BAUMHOF

IPC分类号： H03M13/29 ,  H03M13/25 ,  H03M13/15 ,  H03M13/11 ,  G11B20/18

CPC分类号： H03M13/293 ,  G11B2020/1836 ,  G11B2020/1859 ,  H03M13/1191 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/253 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2927 ,  H03M13/2948 ,  H03M13/2993 ,  H03M13/356 ,  H03M13/3944 ,  H03M13/458 ,  H03M13/618

摘要： A soft input decoding method and a decoder for generalized concatenated (GC) codes. The GC codes are constructed from inner nested block codes, such as binary Bose-Chaudhuri-Hocquenghem, BCH, codes and outer codes, such as Reed-Solomon, RS, codes. In order to enable soft input decoding for the inner block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In one aspect, the present invention applies instead a representation of the block codes based on the trellises of supercodes in order to reduce the memory requirements for the representation of the inner codes. This enables an efficient hardware implementation. In another aspect, there is provided a soft input decoding method and device employing a sequential stack decoding algorithm in combination with list-of-two decoding which is particularly well suited for applications that require very low residual error rates.

公开(公告)号：US20170302299A1

公开(公告)日：2017-10-19

申请号：US15188995

申请日：2016-06-22

申请人： PHISON ELECTRONICS CORP.

发明人： Yu-Hsiang Lin ,  Cheng-Che Yang ,  Shao-Wei Yen ,  Kuo-Hsin Lai

IPC分类号： H03M13/29 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11

CPC分类号： H03M13/2906 ,  G06F11/1012 ,  G06F11/1068 ,  G11C29/52 ,  G11C29/702 ,  H03M13/1102 ,  H03M13/2927 ,  H03M13/3776

摘要： A data processing method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first write data; performing a first stage encoding operation of a low-density parity-check (LDPC) code on the first write data and generating first transition data; performing a second stage encoding operation of the LDPC code on the first transition data and generating a first error correcting code (ECC); receiving second write data; and performing the first stage encoding operation of the LDPC code on the second write data during a time period of performing the second stage encoding operation of the LDPC code on the first transition data. Accordingly, the data processing efficiency corresponding to the LDPC code can be improved.