Biaxial actuator for driving an objective lens in both focusing and
tracking directions
    1.
    发明授权
    Biaxial actuator for driving an objective lens in both focusing and tracking directions 失效
    用于在聚焦和跟踪方向上驱动物镜的双轴致动器

    公开(公告)号:US5519677A

    公开(公告)日:1996-05-21

    申请号:US214697

    申请日:1994-03-18

    IPC分类号: G11B7/09 G11B7/095

    CPC分类号: G11B7/0932

    摘要: An objective lens driving biaxial actuator for driving an objective lens in both a focusing direction and a tracking direction with respect to a recording medium. The biaxial actuator comprises: a movable portion for holding the objective lens; an elastic member having its one end attached to the movable portion for movably supporting the movable portion; a stationary portion fixing the other end of the elastic member; and a balancer disposed at the side of the stationary portion with respect to the objective lens and carried on the movable portion at such a distance that its clearance from the stationary portion may restrict the deformation of the elastic member within an elastic limit. A hinge is interposed between the elastic member and the movable portion for moving the objective lens in the tracking direction.

    摘要翻译: 一种用于驱动双轴致动器的物镜,用于相对于记录介质在聚焦方向和跟踪方向上驱动物镜。 双轴致动器包括:用于保持物镜的可动部分; 弹性构件,其一端附接到所述可动部,用于可移动地支撑所述可动部; 固定所述弹性构件的另一端的固定部; 以及平衡器,其相对于所述物镜设置在所述固定部分的侧面,并以与所述静止部分的间隙限制所述弹性构件在弹性极限内的变形的距离承载在所述可动部分上。 铰链位于弹性构件和可动部分之间,用于在跟踪方向上移动物镜。

    Semiconductor device including internal voltage generation circuit
    2.
    发明授权
    Semiconductor device including internal voltage generation circuit 有权
    半导体器件包括内部电压产生电路

    公开(公告)号:US07656736B2

    公开(公告)日:2010-02-02

    申请号:US11717717

    申请日:2007-03-14

    IPC分类号: G11C5/14

    CPC分类号: G05F1/468 G11C5/025 G11C5/147

    摘要: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

    摘要翻译: 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此,相对于负电压的变化的响应增加。 在待机模式下,通过开关电路连接六个存储器宏的负电压供给线,并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此,可以防止待机电流的增加。

    SEMICONDUCTOR DEVICE INCLUDING INTERNAL VOLTAGE GENERATION CIRCUIT
    3.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING INTERNAL VOLTAGE GENERATION CIRCUIT 失效
    包括内部电压发生电路的半导体器件

    公开(公告)号:US20110182131A1

    公开(公告)日:2011-07-28

    申请号:US13080114

    申请日:2011-04-05

    IPC分类号: G11C5/14

    CPC分类号: G05F1/468 G11C5/025 G11C5/147

    摘要: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

    摘要翻译: 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此,相对于负电压的变化的响应增加。 在待机模式下,通过开关电路连接六个存储器宏的负电压供给线,并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此,可以防止待机电流的增加。

    Semiconductor device undergoing defect detection test
    4.
    发明授权
    Semiconductor device undergoing defect detection test 失效
    半导体器件进行缺陷检测测试

    公开(公告)号:US07408818B2

    公开(公告)日:2008-08-05

    申请号:US11703672

    申请日:2007-02-08

    IPC分类号: G11C11/34

    摘要: A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.

    摘要翻译: 半导体器件具有第一操作模式和第二操作模式,其中提供具有比第一操作模式中更高的电压值的电源。 半导体器件包括具有用于存储数据的存储单元的存储器部分和向存储器部分提供第一电压和第二电压的电源电路部分。 存储器部分基于第一电压和第二电压将数据写入或从存储器单元读取数据,并且电源电路部分在第二操作模式中在第一电压和第二电压之间提供较小的电压差,与第 在第一操作模式下的电压差。

    Semiconductor device including internal voltage generation circuit
    5.
    发明授权
    Semiconductor device including internal voltage generation circuit 失效
    半导体器件包括内部电压产生电路

    公开(公告)号:US08004923B2

    公开(公告)日:2011-08-23

    申请号:US12683838

    申请日:2010-01-07

    IPC分类号: G11C5/14

    CPC分类号: G05F1/468 G11C5/025 G11C5/147

    摘要: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

    摘要翻译: 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此,相对于负电压的变化的响应增加。 在待机模式下,通过开关电路连接六个存储器宏的负电压供给线,并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此,可以防止待机电流的增加。

    Semiconductor device having a plurality of memory modules
    7.
    发明授权
    Semiconductor device having a plurality of memory modules 有权
    具有多个存储器模块的半导体器件

    公开(公告)号:US08837238B2

    公开(公告)日:2014-09-16

    申请号:US13345411

    申请日:2012-01-06

    IPC分类号: G11C7/00 G06F1/32 G11C5/14

    摘要: A semiconductor device which can reduce the peak value of the rush current generated during a transition from resume mode to normal mode. The semiconductor device has a plurality of daisy-chained memory modules. Each of the memory modules includes a memory array, a switch for controlling, in resume mode, source voltage supply to a constituent element of the memory module, and a delay circuit which receives a resume control signal ordering a transition from resume mode to normal mode and outputs a resume control signal delayed from the inputted resume control signal to the memory module of the next stage.

    摘要翻译: 一种半导体器件,其可以减少在从恢复模式转换到正常模式期间产生的冲击电流的峰值。 半导体器件具有多个菊花链式存储器模块。 每个存储器模块包括存储器阵列,用于在恢复模式下控制到存储器模块的组成元件的源电压的开关,以及延迟电路,其接收顺序从恢复模式转换到正常模式的恢复控制信号 并将从输入的恢复控制信号延迟的恢复控制信号输出到下一级的存储器模块。

    Semiconductor device including internal voltage generation circuit
    8.
    发明授权
    Semiconductor device including internal voltage generation circuit 失效
    半导体器件包括内部电压产生电路

    公开(公告)号:US08451678B2

    公开(公告)日:2013-05-28

    申请号:US13080114

    申请日:2011-04-05

    IPC分类号: G11C5/14

    CPC分类号: G05F1/468 G11C5/025 G11C5/147

    摘要: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

    摘要翻译: 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此,相对于负电压的变化的响应增加。 在待机模式下,通过开关电路连接六个存储器宏的负电压供给线,并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此,可以防止待机电流的增加。

    SEMICONDUCTOR DEVICE UNDERGOING DEFECT DETECTION TEST
    9.
    发明申请
    SEMICONDUCTOR DEVICE UNDERGOING DEFECT DETECTION TEST 审中-公开
    缺陷检测测试的半导体器件

    公开(公告)号:US20080298156A1

    公开(公告)日:2008-12-04

    申请号:US12170055

    申请日:2008-07-09

    IPC分类号: G11C5/14

    摘要: A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.

    摘要翻译: 半导体器件具有第一操作模式和第二操作模式,其中提供具有比第一操作模式中更高的电压值的电源。 半导体器件包括具有用于存储数据的存储单元的存储器部分和向存储器部分提供第一电压和第二电压的电源电路部分。 存储器部分基于第一电压和第二电压将数据写入或从存储器单元读取数据,并且电源电路部分在第二操作模式中在第一电压和第二电压之间提供较小的电压差,与第 在第一操作模式下的电压差。

    SEMICONDUCTOR DEVICE INCLUDING INTERNAL VOLTAGE GENERATION CIRCUIT
    10.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING INTERNAL VOLTAGE GENERATION CIRCUIT 失效
    包括内部电压发生电路的半导体器件

    公开(公告)号:US20100109761A1

    公开(公告)日:2010-05-06

    申请号:US12683838

    申请日:2010-01-07

    IPC分类号: G05F1/10

    CPC分类号: G05F1/468 G11C5/025 G11C5/147

    摘要: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

    摘要翻译: 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此,相对于负电压的变化的响应增加。 在待机模式下,通过开关电路连接六个存储器宏的负电压供给线,并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此,可以防止待机电流的增加。