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公开(公告)号：US08059677B1
公开(公告)日：2011-11-15
申请号：US12427960
申请日：2009-04-22
CPC分类号： G06F17/505
摘要： Structures and methods to facilitate channel bundling are disclosed. In one embodiment, signal distribution circuitry includes a data path with at least two registers coupled to adjacent sets of data channels in a bundle of data channel sets. In another embodiment, self-switch circuits allow channels in a bundle of channel-sets to switch from bundle-wide signals to locally generated signals after the bundle-wide signals have been synchronously distributed to all channel sets in the bundle. In a particular embodiment, signal distribution circuitry is used to distribute a divided clock signal. In another particular embodiment, signal distribution circuitry is used to distribute enable signals for first-in first-out circuits (“FIFOs”) located in channels of each data channel set in a channel set bundle. In a particular aspect of an embodiment, FIFO read and write operations across a channel set bundle are initiated such that a difference between read and write pointer signals is the same in each channel set.
摘要翻译： 公开了促进通道捆绑的结构和方法。 在一个实施例中，信号分配电路包括数据路径，其中至少两个寄存器耦合到一组数据信道集合中的相邻数据信道集合。 在另一个实施例中，自交换电路允许信道集合中的信道在束宽信号已经被同步分布到分组中的所有信道集之后从束范围信号切换到本地产生的信号。 在特定实施例中，信号分配电路用于分配分频时钟信号。 在另一特定实施例中，信号分配电路用于分配位于通道组束中的每个数据通道的通道中的先进先出电路（“FIFO”）的使能信号。 在一个实施例的一个特定方面，跨越信道集束的FIFO读和写操作被启动，使得每个信道集合中读指针信号和写指针信号之间的差异是相同的。
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2.发明授权CDR control architecture for robust low-latency exit from the power-saving mode of an embedded CDR in a programmable integrated circuit device 有权CDR控制架构，用于强大的低延迟退出可编程集成电路设备中嵌入式CDR的省电模式公开(公告)号：US08291255B1
公开(公告)日：2012-10-16
申请号：US13082162
申请日：2011-04-07
CPC分类号： G06F13/4295 , H04L7/0083 , H04L7/033 , H04L7/10 , Y02D10/14 , Y02D10/151
摘要： Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its “lock-to-reference” (“LTR”) state and its normal “lock-to-data” (“LTD”) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.
摘要翻译： 可编程集成电路设备上的高速串行接口的时钟数据恢复（CDR）电路在接口的接收机的电气空闲周期内切换其锁定参考（LTR）状态与其正常的锁定 - 数据（LTD）状态。 无论何时在这个切换模式下，CDR电路切换到LTD状态，它保持在该状态一段预定的间隔，然后返回到LTR状态，除非在它处于LTD状态时，它接收来自接收器中其他地方的信号 已经接收到数据并发生字节同步。 预定的切换间隔优选地足够长以获得LTR锁定以使频率漂移最小化，但足够短以避免对同步信号的检测的不必要的延迟。 优选地，该间隔可由用户在由可编程设备的表征确定的限度内编程。 从而避免了不可靠的模拟信号检测。
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3.发明授权CDR control architecture for robust low-latency exit from the power-saving mode of an embedded CDR in a programmable integrated circuit device 有权CDR控制架构，用于强大的低延迟退出可编程集成电路设备中嵌入式CDR的省电模式公开(公告)号：US07925913B1
公开(公告)日：2011-04-12
申请号：US11857141
申请日：2007-09-18
CPC分类号： G06F13/4295 , H04L7/0083 , H04L7/033 , H04L7/10 , Y02D10/14 , Y02D10/151
摘要： Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its “lock-to-reference” (“LTR”) state and its normal “lock-to-data” (“LTD”) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.
摘要翻译： 可编程集成电路设备上的高速串行接口的时钟数据恢复（CDR）电路在接口的接收机的电空闲周期之间切换其“锁定参考”（“LTR”）状态和 其正常的“锁定数据”（“LTD”）状态。 无论何时在这个切换模式下，CDR电路切换到LTD状态，它保持在该状态一段预定的间隔，然后返回到LTR状态，除非在它处于LTD状态时，它接收来自接收器中其他地方的信号 已经接收到数据并发生字节同步。 预定的切换间隔优选地足够长以获得LTR锁定以使频率漂移最小化，但足够短以避免对同步信号的检测的不必要的延迟。 优选地，该间隔可由用户在由可编程设备的表征确定的限度内编程。 从而避免了不可靠的模拟信号检测。
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