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1.发明授权CDR control architecture for robust low-latency exit from the power-saving mode of an embedded CDR in a programmable integrated circuit device 有权CDR控制架构，用于强大的低延迟退出可编程集成电路设备中嵌入式CDR的省电模式公开(公告)号：US07925913B1
公开(公告)日：2011-04-12
申请号：US11857141
申请日：2007-09-18
CPC分类号： G06F13/4295 , H04L7/0083 , H04L7/033 , H04L7/10 , Y02D10/14 , Y02D10/151
摘要： Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its “lock-to-reference” (“LTR”) state and its normal “lock-to-data” (“LTD”) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.
摘要翻译： 可编程集成电路设备上的高速串行接口的时钟数据恢复（CDR）电路在接口的接收机的电空闲周期之间切换其“锁定参考”（“LTR”）状态和 其正常的“锁定数据”（“LTD”）状态。 无论何时在这个切换模式下，CDR电路切换到LTD状态，它保持在该状态一段预定的间隔，然后返回到LTR状态，除非在它处于LTD状态时，它接收来自接收器中其他地方的信号 已经接收到数据并发生字节同步。 预定的切换间隔优选地足够长以获得LTR锁定以使频率漂移最小化，但足够短以避免对同步信号的检测的不必要的延迟。 优选地，该间隔可由用户在由可编程设备的表征确定的限度内编程。 从而避免了不可靠的模拟信号检测。
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2.发明授权CDR control architecture for robust low-latency exit from the power-saving mode of an embedded CDR in a programmable integrated circuit device 有权CDR控制架构，用于强大的低延迟退出可编程集成电路设备中嵌入式CDR的省电模式公开(公告)号：US08291255B1
公开(公告)日：2012-10-16
申请号：US13082162
申请日：2011-04-07
CPC分类号： G06F13/4295 , H04L7/0083 , H04L7/033 , H04L7/10 , Y02D10/14 , Y02D10/151
摘要： Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its “lock-to-reference” (“LTR”) state and its normal “lock-to-data” (“LTD”) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.
摘要翻译： 可编程集成电路设备上的高速串行接口的时钟数据恢复（CDR）电路在接口的接收机的电气空闲周期内切换其锁定参考（LTR）状态与其正常的锁定 - 数据（LTD）状态。 无论何时在这个切换模式下，CDR电路切换到LTD状态，它保持在该状态一段预定的间隔，然后返回到LTR状态，除非在它处于LTD状态时，它接收来自接收器中其他地方的信号 已经接收到数据并发生字节同步。 预定的切换间隔优选地足够长以获得LTR锁定以使频率漂移最小化，但足够短以避免对同步信号的检测的不必要的延迟。 优选地，该间隔可由用户在由可编程设备的表征确定的限度内编程。 从而避免了不可靠的模拟信号检测。
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3.发明授权Integrated hard-wired or partly hard-wired CRC generation and/or checking architecture for a physical coding sublayer in a programmable logic device 有权用于可编程逻辑器件中的物理编码子层的集成硬连线或部分硬连线CRC生成和/或检查架构公开(公告)号：US07627806B1
公开(公告)日：2009-12-01
申请号：US11436463
申请日：2006-05-17
IPC分类号： H03M13/09
CPC分类号： H04L1/0052 , H03M13/09 , H03M13/6516 , H04L1/0061
摘要： A programmable logic integrated circuit device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry that is at least partly hard-wired to perform at least some functional aspects of the HSSI operations. Cyclic redundancy check (CRC) generation and/or checking circuitry is now included in this HSSI circuitry, and again, this CRC circuitry is at least partly hard-wired to perform at least some functional aspects of its operations(s).
摘要翻译： 可编程逻辑集成电路器件（“PLD”）包括至少部分硬接线以执行HSSI操作的至少一些功能方面的高速串行接口（“HSSI”）电路。 循环冗余校验（CRC）生成和/或检查电路现在包括在该HSSI电路中，并且再次，该CRC电路至少部分地硬接线以执行其操作的至少一些功能方面。
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4.发明授权Multi-protocol configurable transceiver including configurable deskew in an integrated circuit 有权多协议可配置收发器，包括集成电路中的可配置的偏移校正公开(公告)号：US09531646B1
公开(公告)日：2016-12-27
申请号：US12632744
申请日：2009-12-07
申请人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee , Vinson Chan
发明人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee , Vinson Chan
IPC分类号： G06F3/00 , H04L12/861 , G06F5/10
摘要： Embodiments include a configurable multi-protocol transceiver including configurable deskew circuitry. In one embodiment, configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. In another embodiment, configurable circuitry is adapted to control a deskew character transmit insertion frequency. In another embodiment, a programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an alignment lock condition. In another embodiment, configurable circuitry is adaptable to select between logic and routing resources in the transceiver and logic and routing resources in a core of the IC in which the transceiver is implemented for controlling at least certain deskew operations. In another embodiment, configurable selection circuitry allows deskew processing to occur in a data path either before or after clock compensation processing depending on a communication protocol for which the transceiver is to be configured.
摘要翻译： 实施例包括可配置的多协议收发器，包括可配置的偏移电路。 在一个实施例中，可配置电路适于控制多个缓冲器的允许数据深度。 在另一个实施例中，可配置电路适于控制偏斜字符传输插入频率。 在另一个实施例中，可编程状态机适于根据用于实现对准锁定状态的可选条件来控制读取和写入指针。 在另一个实施例中，可配置电路适于在收发器中的逻辑和路由资源之间选择逻辑，并且在IC的核心中布线资源，其中实现收发器用于控制至少某些去歪斜操作。 在另一个实施例中，可配置的选择电路允许在时钟补偿处理之前或之后在数据路径中进行偏移处理，这取决于要配置收发器的通信协议。
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5.发明授权Method and system for operating a communication circuit during a low-power state 有权在低功率状态下操作通信电路的方法和系统公开(公告)号：US09049120B1
公开(公告)日：2015-06-02
申请号：US13175740
申请日：2011-07-01
申请人： Divya Vijayaraghavan , Chong H. Lee
发明人： Divya Vijayaraghavan , Chong H. Lee
CPC分类号： H04L41/0833 , H04L12/40013 , Y02B60/35
摘要： A method and system for operating a communication circuit during periods of reduced energy consumption are disclosed. Data may be transmitted over a communication link from a first device to a second device in a low-power state. The data may be used by the second device to update coefficients and/or synchronize the receiver of the second device to a transmitter of the first device, thereby enabling a more efficient or rapid transition from the low-power state to an active state. A transmitter of the first device and a receiver of the second device may be activated before transmission of the data and deactivated after transmission of the data. In this manner, a receiver of the second device may be refreshed to enable a more efficient transition from the low-power state to an active state.
摘要翻译： 公开了一种在降低能量消耗期间操作通信电路的方法和系统。 数据可以通过通信链路从低功率状态从第一设备传输到第二设备。 该数据可以被第二设备用来更新系统和/或将第二设备的接收机同步到第一设备的发射机，从而能够从低功率状态到活动状态的更有效或快速的转变。 第一设备的发射机和第二设备的接收机可以在传输数据之前激活，并且在传输数据之后停用。 以这种方式，可以刷新第二设备的接收机，以便能够从低功率状态到活动状态的更有效的转变。
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6.发明授权Flexible interface for stacked protocol in a programmable integrated circuit device 有权可编程集成电路器件中堆叠协议的灵活接口公开(公告)号：US08458383B1
公开(公告)日：2013-06-04
申请号：US11848016
申请日：2007-08-30
申请人： Curt Wortman , Chong H. Lee , Divya Vijayaraghavan , Ning Xue
发明人： Curt Wortman , Chong H. Lee , Divya Vijayaraghavan , Ning Xue
CPC分类号： G06F13/4059 , Y02D10/14 , Y02D10/151
摘要： On programmable device, each layer of a programmable interface, for a protocol which has a protocol stack including at least a physical layer, a data link layer and a transaction layer, is selectably bypassable. When a layer is bypassed, all other layers downstream of that layer also are bypassed. In addition, the interface may be divided into different clock domains running at different clock rates, reflecting clock rates within the programmable device and outside the programmable device. Layers may be bypassed to allow a user to substitute a custom layer in programmable logic, or to substitute an updated layer for debugging purposes.
摘要翻译： 在可编程设备上，用于具有包括至少物理层，数据链路层和事务层的协议栈的协议的可编程接口的每层可选择地旁路。 当旁路一层时，该层下游的所有其他层也被旁路。 此外，该接口可以被划分为以不同的时钟速率运行的不同的时钟域，反映了可编程器件内部和可编程器件外部的时钟速率。 可以绕过图层以允许用户替换可编程逻辑中的自定义层，或者替换更新的层进行调试。
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7.发明授权Multi-protocol channel-aggregated configurable transceiver in an integrated circuit 有权集成电路中的多协议通道聚合可配置收发器公开(公告)号：US08165191B2
公开(公告)日：2012-04-24
申请号：US12288178
申请日：2008-10-17
申请人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee
发明人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee
CPC分类号： H04B1/005 , G06F13/385 , H04L69/12 , H04L69/18
摘要： Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer (“PCS”) circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer (“PMA”) circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent (“PMD”) sub-layer circuitry.
摘要翻译： 本公开的实施例包括包括接收和/或发送电路的可配置布置的多协议收发器。 可以选择性地配置示例性收发器以有效地发送和/或接收对应于多个高速通信协议中的选择一个的数据通信。 所公开的另一更具体的实施例包括通过链路范围物理编码子层（“PCS”）电路的可配置数据路径，包括链路范围时钟补偿，编码/解码以及加扰/解扰频电路和通道条带/去条纹电路; 可配置数据路径还包括通道宽电路，包括时钟补偿，编码/解码，接收块同步和物理介质访问子层（“PMA”）电路，并且还包括耦合到物理介质的位复用/解复用电路 从属（“PMD”）子层电路。
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公开(公告)号：US09170952B1
公开(公告)日：2015-10-27
申请号：US13338707
申请日：2011-12-28
申请人： Divya Vijayaraghavan , Vinson Chan , Keith Duwel , Chong H. Lee
发明人： Divya Vijayaraghavan , Vinson Chan , Keith Duwel , Chong H. Lee
IPC分类号： G06F13/00 , G06F12/02 , G06F12/08 , G06F13/12 , G06F13/14 , G06F11/00 , H01L25/00 , H04J3/06
CPC分类号： G06F12/0862 , G06F13/00 , H03K19/17744
摘要： A configurable interface includes a transmitter module and a receiver module, each configured to operate according to at least three different interface standards. The configurable interface further includes an interface module configured to determine a physical medium attachment (PMA) standard of a PMA coupled to the configurable interface and activate at least one component of the configurable interface based on the PMA standard. In an arrangement, the device interface supports a CAUI-4 standard.
摘要翻译： 可配置接口包括发射器模块和接收器模块，每个发送器模块和接收器模块被配置为根据至少三个不同的接口标准进行操作。 所述可配置接口还包括接口模块，所述接口模块被配置为确定耦合到所述可配置接口的PMA的物理介质连接（PMA）标准，并基于所述PMA标准激活所述可配置接口的至少一个组件。 在这种安排中，设备接口支持CAUI-4标准。
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9.发明授权Method and system for transitioning a communication circuit to a low-power state 有权将通信电路转换为低功率状态的方法和系统公开(公告)号：US08989284B1
公开(公告)日：2015-03-24
申请号：US13175749
申请日：2011-07-01
申请人： Divya Vijayaraghavan , Chong H. Lee
发明人： Divya Vijayaraghavan , Chong H. Lee
IPC分类号： H04L27/00
CPC分类号： H04W52/0229 , H04W52/0235 , H04W52/028 , Y02D70/00
摘要： A method and system for transitioning a communication circuit to a low-power state are disclosed. Where a first device and a second device communicate over a communication link, the first device may initiate a transition from an active state to a low-power state to conserve energy. A symbol may be encoded by the first device in data and transmitted to the second device. The first device may deactivate one or more components when entering the low-power state. Additionally, responsive to receiving and decoding the symbol, the second device may deactivate one or more components when entering the low-power state. In this manner, energy consumption of one or more components can be reduced and a low-power state may be entered to conserve energy.
摘要翻译： 公开了一种将通信电路转换为低功率状态的方法和系统。 在第一设备和第二设备通过通信链路进行通信的情况下，第一设备可以发起从活动状态到低功率状态的转换以节省能量。 符号可以由数据中的第一设备编码并被发送到第二设备。 当进入低功率状态时，第一设备可以去激活一个或多个组件。 另外，响应于符号的接收和解码，第二设备可以在进入低功率状态时停用一个或多个组件。 以这种方式，可以减少一个或多个部件的能量消耗，并且可以输入低功率状态以节省能量。
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公开(公告)号：US08630198B1
公开(公告)日：2014-01-14
申请号：US12983180
申请日：2010-12-31
IPC分类号： G01R31/08
CPC分类号： H04L25/03885 , H04B3/04 , H04B3/32 , H04L25/03343
摘要： One embodiment relates to an integrated circuit configured to perform dynamic transmit equalization of a bi-directional lane. The integrated circuit including an interface between the physical coding and media access control circuitry, and an equalization control circuit which is external to the physical coding circuitry and which is configured to perform the dynamic transmit equalization using said interface. Another embodiment relates to a transceiver circuit which includes physical coding circuitry and media access control circuitry. The transceiver circuit further includes an interface between the physical coding circuitry and the media access control circuitry and an equalization controller which is external to the physical coding circuitry and which is configured to perform dynamic transmit equalization using said interface. The interface is configured to provide transmit coefficient data in a time-multiplexed signal format from the media access control circuitry to the physical coding circuitry. Other embodiments, aspects, and features are also disclosed.
摘要翻译： 一个实施例涉及被配置为执行双向通道的动态发送均衡的集成电路。 该集成电路包括物理编码和媒体访问控制电路之间的接口，以及在物理编码电路外部的配置成使用所述接口执行动态发送均衡的均衡控制电路。 另一个实施例涉及一种包括物理编码电路和媒体访问控制电路的收发器电路。 收发器电路还包括物理编码电路和媒体访问控制电路之间的接口以及在物理编码电路之外的均衡控制器，并且被配置为使用所述接口执行动态发送均衡。 接口被配置为以时间复用的信号格式提供从媒体访问控制电路到物理编码电路的传输系数数据。 还公开了其它实施例，方面和特征。
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