公开(公告)号：US20130246834A1

公开(公告)日：2013-09-19

申请号：US13729125

申请日：2012-12-28

申请人： Ken Keon Shim ,  Hoi Jin Lee ,  Gun Ok Jung

发明人： Ken Keon Shim ,  Hoi Jin Lee ,  Gun Ok Jung

IPC分类号： H03K19/096 ,  G06F1/08

CPC分类号： H03K19/096 ,  G06F1/08 ,  H03K19/0963

摘要： A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal.

摘要翻译： 多米诺逻辑电路包括在锁存器和触发器之间串联连接的多个多米诺逻辑级和产生具有第一占空比的时钟信号的时钟信号发生器和具有第二占空比的触发器时钟信号。 锁存器和多米诺逻辑级分别响应于从第一时钟信号导出的多米诺骨牌时钟信号而工作。 触发器响应于触发器时钟信号而工作。

公开(公告)号：US08810279B2

公开(公告)日：2014-08-19

申请号：US13729125

申请日：2012-12-28

申请人： Ken Keon Shim ,  Hoi Jin Lee ,  Gun Ok Jung

发明人： Ken Keon Shim ,  Hoi Jin Lee ,  Gun Ok Jung

IPC分类号： H03K19/00

CPC分类号： H03K19/096 ,  G06F1/08 ,  H03K19/0963

摘要： A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal.

摘要翻译： 多米诺逻辑电路包括串联连接在锁存器和触发器之间的多个多米诺逻辑级和产生具有第一占空比的时钟信号的时钟信号发生器和具有第二占空比的触发器时钟信号。 锁存器和多米诺逻辑级分别响应于从第一时钟信号导出的多米诺骨牌时钟信号而工作。 触发器响应于触发器时钟信号而工作。