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    Pseudo-static domino logic circuit and apparatuses including same
    2.
    发明授权
    Pseudo-static domino logic circuit and apparatuses including same 有权
    伪静态多米诺逻辑电路及包括其的设备

    公开(公告)号：US08810279B2

    公开(公告)日：2014-08-19

    申请号：US13729125

    申请日：2012-12-28

    申请人： Ken Keon Shim ,  Hoi Jin Lee ,  Gun Ok Jung

    发明人： Ken Keon Shim ,  Hoi Jin Lee ,  Gun Ok Jung

    IPC分类号： H03K19/00

    CPC分类号： H03K19/096 ,  G06F1/08 ,  H03K19/0963

    摘要： A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal.

    摘要翻译： 多米诺逻辑电路包括串联连接在锁存器和触发器之间的多个多米诺逻辑级和产生具有第一占空比的时钟信号的时钟信号发生器和具有第二占空比的触发器时钟信号。 锁存器和多米诺逻辑级分别响应于从第一时钟信号导出的多米诺骨牌时钟信号而工作。 触发器响应于触发器时钟信号而工作。

    Domino logic circuits and pipelined domino logic circuits
    3.
    发明授权
    Domino logic circuits and pipelined domino logic circuits 有权
    多米诺逻辑电路和流水线多米诺逻辑电路

    公开(公告)号：US08542033B2

    公开(公告)日：2013-09-24

    申请号：US13234811

    申请日：2011-09-16

    申请人： Hyoung-Wook Lee ,  Gun-Ok Jung ,  Suhwan Kim ,  Ah-Reum Kim ,  Rahul Singh

    发明人： Hyoung-Wook Lee ,  Gun-Ok Jung ,  Suhwan Kim ,  Ah-Reum Kim ,  Rahul Singh

    IPC分类号： H03K19/00

    CPC分类号： H03K19/0966

    摘要： A domino logic circuit includes a first evaluation unit, a second evaluation unit and an output unit. The first evaluation unit precharges a first dynamic node, discharges a footer node in a first phase of a clock signal, and evaluates a plurality of input signals to determine a logic level of the first dynamic node in a second phase of the clock signal. The second evaluation unit precharges a second dynamic node in the first phase of the clock signal, and determines a logic level of the second dynamic node in response to a logic level of the footer node in the second phase of the clock signal. The output unit provides an output signal having a logic level according to levels of a first voltage of the first dynamic node and a second voltage of the second dynamic node.

    摘要翻译： 多米诺逻辑电路包括第一评估单元，第二评估单元和输出单元。 第一评估单元对第一动态节点进行预充电，在时钟信号的第一阶段放电页脚节点，并且评估多个输入信号以在时钟信号的第二阶段中确定第一动态节点的逻辑电平。 第二评估单元在时钟信号的第一阶段中对第二动态节点进行预充电，并且响应于时钟信号的第二阶段中的页脚节点的逻辑电平来确定第二动态节点的逻辑电平。 输出单元提供具有根据第一动态节点的第一电压的电平和第二动态节点的第二电压的逻辑电平的输出信号。

    Clock skew controller and integrated circuit including the same
    4.
    发明申请
    Clock skew controller and integrated circuit including the same 有权
    时钟偏移控制器和集成电路包括相同的

    公开(公告)号：US20080204103A1

    公开(公告)日：2008-08-28

    申请号：US12071635

    申请日：2008-02-25

    申请人： Gun-Ok Jung ,  Chung-Hee Kim

    发明人： Gun-Ok Jung ,  Chung-Hee Kim

    IPC分类号： H03H11/26 ,  G06F1/04

    CPC分类号： G06F1/10 ,  H03K5/133 ,  H03K5/15013

    摘要： A clock skew controller for adjusting a skew between a first clock, which is input to a first clock mesh, and a second clock mesh input to a second clock mesh, includes a pulse generator adapted to output a pulse signal corresponding to a delay time between a first output clock output from the first clock mesh and a second output clock output from the second clock mesh, a pulse width detector adapted to generate a digital signal corresponding to a pulse width of the pulse signal, and a clock delay adjuster adapted to delay one of the first and second clocks by a time corresponding to the digital signal

    摘要翻译： 用于调整输入到第一时钟网格的第一时钟与第二时钟网格的第二时钟网格输入之间的偏斜的时钟偏移控制器包括脉冲发生器，其适于输出对应于延迟时间之间的脉冲信号 从第一时钟网格输出的第一输出时钟和从第二时钟网格输出的第二输出时钟，适于产生对应于脉冲信号的脉冲宽度的数字信号的脉冲宽度检测器，以及适于延迟的时钟延迟调整器 第一和第二时钟之一对应于数字信号

    Accessing semiconductor memory device according to an address and additional access information
    5.
    发明申请
    Accessing semiconductor memory device according to an address and additional access information 失效
    根据地址和附加访问信息访问半导体存储器件

    公开(公告)号：US20070195598A1

    公开(公告)日：2007-08-23

    申请号：US11705485

    申请日：2007-02-12

    申请人： Gi-Ho Park ,  Gun-Ok Jung

    发明人： Gi-Ho Park ,  Gun-Ok Jung

    IPC分类号： G11C16/04 ,  G11C5/14 ,  G11C8/00 ,  G11C11/34 ,  G11C7/02

    CPC分类号： G11C8/10 ,  G11C11/413 ,  G11C16/08

    摘要： A semiconductor memory device includes a memory cell array, a decoder, and an access control unit. The decoder generates a word line voltage according to an address for a plurality of memory cells in the memory cell array. The access control unit controls access to the plurality of memory cells according to the word line voltage and additional access information separate from the address.

    摘要翻译： 半导体存储器件包括存储单元阵列，解码器和访问控制单元。 解码器根据存储单元阵列中的多个存储单元的地址产生字线电压。 访问控制单元根据字线电压和与该地址分离的附加访问信息控制对多个存储器单元的访问。

    PSEUDO-STATIC DOMINO LOGIC CIRCUIT AND APPARATUSES INCLUDING SAME
    6.
    发明申请
    PSEUDO-STATIC DOMINO LOGIC CIRCUIT AND APPARATUSES INCLUDING SAME 有权
    PSEUDO-STATIC DOMINO LOGIC CIRCUIT和包括其中的设备

    公开(公告)号：US20130246834A1

    公开(公告)日：2013-09-19

    申请号：US13729125

    申请日：2012-12-28

    申请人： Ken Keon Shim ,  Hoi Jin Lee ,  Gun Ok Jung

    发明人： Ken Keon Shim ,  Hoi Jin Lee ,  Gun Ok Jung

    IPC分类号： H03K19/096 ,  G06F1/08

    CPC分类号： H03K19/096 ,  G06F1/08 ,  H03K19/0963

    摘要： A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal.

    摘要翻译： 多米诺逻辑电路包括在锁存器和触发器之间串联连接的多个多米诺逻辑级和产生具有第一占空比的时钟信号的时钟信号发生器和具有第二占空比的触发器时钟信号。 锁存器和多米诺逻辑级分别响应于从第一时钟信号导出的多米诺骨牌时钟信号而工作。 触发器响应于触发器时钟信号而工作。

    FOOTER-LESS NP DOMINO LOGIC CIRCUIT AND RELATED APPARATUS
    7.
    发明申请
    FOOTER-LESS NP DOMINO LOGIC CIRCUIT AND RELATED APPARATUS 有权
    无袖NP逻辑逻辑电路及相关设备

    公开(公告)号：US20130246819A1

    公开(公告)日：2013-09-19

    申请号：US13795852

    申请日：2013-03-12

    申请人： Ken Keon Shin ,  Hoi Jin Lee ,  Gun Ok Jung ,  Min Su Kim

    发明人： Ken Keon Shin ,  Hoi Jin Lee ,  Gun Ok Jung ,  Min Su Kim

    IPC分类号： G06F1/32 ,  G06F1/04 ,  H03K19/00

    CPC分类号： G06F1/32 ,  G06F1/04 ,  H03K19/0008 ,  H03K19/0963

    摘要： A domino logic circuit includes a pre-charge circuit pre-charging a first dynamic node in response to a clock signal, a first logic network determining a logic level of the first dynamic node in response to first data signals, an inverter receiving the clock signal, a discharge circuit discharging a second dynamic node in response to an output signal of the inverter, and a second logic network determining a logic level of the second dynamic node in response to at least one second data signal and an output signal of the first dynamic node.

    摘要翻译： 多米诺骨牌逻辑电路包括响应于时钟信号对第一动态节点预充电的预充电电路，第一逻辑网络响应于第一数据信号确定第一动态节点的逻辑电平，反相器接收时钟信号 响应于逆变器的输出信号而放电第二动态节点的放电电路，以及响应于至少一个第二数据信号和第一动态节点的输出信号确定第二动态节点的逻辑电平的第二逻辑网络 节点。

    Clock skew controller and integrated circuit including the same
    8.
    发明授权
    Clock skew controller and integrated circuit including the same 有权
    时钟偏移控制器和集成电路包括相同的

    公开(公告)号：US07971088B2

    公开(公告)日：2011-06-28

    申请号：US12071635

    申请日：2008-02-25

    申请人： Gun-Ok Jung ,  Chung-Hee Kim

    发明人： Gun-Ok Jung ,  Chung-Hee Kim

    IPC分类号： G06F1/04

    CPC分类号： G06F1/10 ,  H03K5/133 ,  H03K5/15013

    摘要： A clock skew controller for adjusting a skew between a first clock, which is input to a first clock mesh, and a second clock mesh input to a second clock mesh, includes a pulse generator adapted to output a pulse signal corresponding to a delay time between a first output clock output from the first clock mesh and a second output clock output from the second clock mesh, a pulse width detector adapted to generate a digital signal corresponding to a pulse width of the pulse signal, and a clock delay adjuster adapted to delay one of the first and second clocks by a time corresponding to the digital signal.

    摘要翻译： 用于调整输入到第一时钟网格的第一时钟与第二时钟网格的第二时钟网格输入之间的偏斜的时钟偏移控制器包括脉冲发生器，其适于输出对应于延迟时间之间的脉冲信号 从第一时钟网格输出的第一输出时钟和从第二时钟网格输出的第二输出时钟，适于产生对应于脉冲信号的脉冲宽度的数字信号的脉冲宽度检测器，以及适于延迟的时钟延迟调整器 第一和第二时钟之一对应于数字信号。

    Leakage current detection circuit and leakage current comparison circuit
    9.
    发明授权
    Leakage current detection circuit and leakage current comparison circuit 有权
    泄漏电流检测电路和漏电流比较电路

    公开(公告)号：US07944267B2

    公开(公告)日：2011-05-17

    申请号：US12752389

    申请日：2010-04-01

    申请人： Gun-Ok Jung

    发明人： Gun-Ok Jung

    IPC分类号： H03K17/687

    CPC分类号： G01R31/275 ,  G01R31/2621 ,  G01R31/3008 ,  H03K2217/0036

    摘要： A leakage current measurement circuit measuring a substrate leakage current and a gate leakage current in response to a variation in the size of an MOS transistor and a leakage current comparison circuit judging which one of the substrate leakage current and the gate leakage current is dominant. The leakage current measurement circuit includes a charge supply, a leakage current generator and a detection signal generator. The leakage current comparison circuit includes a charge supply, a leakage current comparator and a detection signal generator.

    摘要翻译： 泄漏电流测量电路，其响应于MOS晶体管和泄漏电流比较电路的尺寸变化来测量衬底漏电流和栅极漏电流，判断衬底泄漏电流和栅极漏电流中哪一个占优势。 泄漏电流测量电路包括电荷源，漏电流发生器和检测信号发生器。 泄漏电流比较电路包括电荷源，漏电流比较器和检测信号发生器。

    Frequency multiplier capable of adjusting duty cycle of a clock and method used therein
    10.
    发明授权
    Frequency multiplier capable of adjusting duty cycle of a clock and method used therein 有权
    能够调整时钟占空比的频率倍增器及其中使用的方法

    公开(公告)号：US07180340B2

    公开(公告)日：2007-02-20

    申请号：US10655024

    申请日：2003-09-05

    申请人： Gun-Ok Jung ,  Sung-Bae Park

    发明人： Gun-Ok Jung ,  Sung-Bae Park

    IPC分类号： H03B19/00

    CPC分类号： H03K5/00006 ,  G06F7/68 ,  H03K5/1565 ,  H03L7/0814

    摘要： Provided is a frequency multiplier including a delay circuit, an XOR gate, and a control circuit and a method of operating such a frequency multiplier to adjust the duty cycle of a clock signal. During operation of the frequency multiplier the delay circuit receives a first clock signal and generates a delayed clock signal. The XOR gate receives the first clock signal and the delayed clock signal, performs an XOR operation on the received signals and outputs a second clock signal that has a frequency that is a multiple of the first clock signal. The control circuit monitors the phase difference between the first clock signal and the delayed clock signal and outputs a control signal corresponding to the detected phase difference to the delay circuit to adjust the time delay applied to the first clock signal by the delay circuit.

    摘要翻译： 提供了包括延迟电路，异或门和控制电路的倍频器，以及操作这种倍频器以调整时钟信号的占空比的方法。 在倍频器的操作期间，延迟电路接收第一时钟信号并产生延迟的时钟信号。 异或门接收第一时钟信号和延迟的时钟信号，对接收的信号执行异或运算，并输出具有第一时钟信号倍数的频率的第二时钟信号。 控制电路监视第一时钟信号和延迟的时钟信号之间的相位差，并将对应于检测到的相位差的控制信号输出到延迟电路，以通过延迟电路调整施加到第一时钟信号的时间延迟。