摘要:
The radar system includes: a transmission circuit transmitting the radar waves via a transmission antenna; a receiving circuit receiving the reflected waves via a receiving antenna; a delay line having an end connected to aid transmission circuit and the other end connected to said receiving circuit, which delays the radar waves by a predetermined delay amount; a correlation circuit/coherent detection circuit which detects a waveform having a strength equal to or higher than a predetermined strength, from a signal provided from said receiving circuit which obtains the signal from the reflected waves or the delayed radar waves; and a level decision circuit which judges, during self-diagnosis, whether or not the detected waveform is a waveform of the delayed radar wave according to the predetermined delay amount, and if the waveform is not the waveform of the delayed radar wave, determines that abnormality occurs in said radar system.
摘要:
The spread spectrum radar apparatus in the present invention (i) includes: a transmission code generator (110); a reception code generator (121) generating a reception code obtained by delaying a transmission code; a spread modulator (112) spread-modulating a signal generated by a local oscillator (111) using the transmission code; a transmission antenna (113) transmitting the spread-modulated signal; a reception antenna (120) receiving a signal; a spread demodulator (122) demodulating the signal using the reception code to provide a correlation signal; a mixer (123) mixing the correlation signal and the signal generated by the local oscillator (111) to generate a radar signal; a virtual image determining unit (130) determining a virtual image; and a radar signal calculation device (160) calculating the radar signal using a virtual image determination signal, and (ii) adds a calculation and an offset signal for suppressing a peak intensity of the virtual image when the virtual image occurs.
摘要:
The code generation apparatus includes: a clock generation unit (160) which generates a clock signal of a first frequency; a timing control unit (130) which generates a timing signal of a second frequency lower than the first frequency; a code table storage unit (120) in which a plurality of code sequences serving as a source for a pseudo-noise code is stored; an address control unit (110) which selects, according to the timing signal, a code sequence to be read, from among a plurality of code sequences; a partial code sequence extraction unit (140) which extracts, as a partial code sequence, a code of a predetermined length, from the code sequence to be read; and a parallel-series conversion unit (150) which outputs the partial code sequence by one bit at a time, according to the clock signal.
摘要:
The spread spectrum radar apparatus in the present invention (i) includes: a transmission code generator (110); a reception code generator (121) generating a reception code obtained by delaying a transmission code; a spread modulator (112) spread-modulating a signal generated by a local oscillator (111) using the transmission code; a transmission antenna (113) transmitting the spread-modulated signal; a reception antenna (120) receiving a signal; a spread demodulator (122) demodulating the signal using the reception code to provide a correlation signal; a mixer (123) mixing the correlation signal and the signal generated by the local oscillator (111) to generate a radar signal; a virtual image determining unit (130) determining a virtual image; and a radar signal calculation device (160) calculating the radar signal using a virtual image determination signal, and (ii) adds a calculation and an offset signal for suppressing a peak intensity of the virtual image when the virtual image occurs.
摘要:
The code generation apparatus includes: a clock generator which generates a clock signal of a first frequency; a timing controller which generates a timing signal of a second frequency lower than the first frequency; a code table storage in which a plurality of code sequences serving as a source for a pseudo-noise code is stored; an address controller which selects, according to the timing signal, a code sequence to be read, from among a plurality of code sequences; a partial code sequence extractor which extracts, as a partial code sequence, a code of a predetermined length, from the code sequence to be read; and a parallel-series convertor which outputs the partial code sequence one bit at a time, according to the clock signal.