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    HIGH FREQUENCY SIGNAL PROCESSING DEVICE
    1.
    发明申请
    HIGH FREQUENCY SIGNAL PROCESSING DEVICE 有权
    高频信号处理装置

    公开(公告)号：US20120019328A1

    公开(公告)日：2012-01-26

    申请号：US13165879

    申请日：2011-06-22

    申请人： Kenichi SHIBATA ,  Toshiya UOZUMI

    发明人： Kenichi SHIBATA ,  Toshiya UOZUMI

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0891 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265

    摘要： A high frequency signal processing device is capable of carrying out high-accuracy modulation by a PLL circuit. A digital loop is configured in addition to an analog loop having, for example, a phase frequency detector, a charge pump circuit, and a loop filter. A digital calibration circuit is provided which searches for the optimal code set to a capacitor bank upon frequency modulation. Upon the search for the optimal code, a calibration controller first sets a division ratio based on a center frequency to a divider and determines the value of a voltage control signal using the analog loop. Then, the loop filter holds the value of the voltage control signal therein, and a division ratio corresponding to a “center frequency+modulated portion” is set to the divider, thereby operating the digital loop. The optimal code is obtained by a convergent value of the digital loop.

    摘要翻译： 高频信号处理装置能够通过PLL电路进行高精度的调制。 除了具有例如相位频率检测器，电荷泵电路和环路滤波器的模拟环路之外，配置数字环路。 提供了一种数字校准电路，其在频率调制时搜索对电容器组设置的最佳代码。 在搜索最佳代码时，校准控制器首先根据中心频率将分频比设置为分频器，并使用模拟环路确定电压控制信号的值。 然后，环路滤波器保持其中的电压控制信号的值，并且将对应于“中心频率+调制部分”的分频比设置为分频器，从而操作数字环路。 最佳代码是通过数字循环的收敛值获得的。

    FILTER CIRCUIT AND RECEIVER USING THE SAME
    4.
    发明申请
    FILTER CIRCUIT AND RECEIVER USING THE SAME 有权
    滤波电路和接收器

    公开(公告)号：US20110026507A1

    公开(公告)日：2011-02-03

    申请号：US12789771

    申请日：2010-05-28

    申请人： Yusaku KATSUBE ,  Junichi TAKAHASHI ,  Masaaki YAMADA ,  Toshihito HABUKA ,  Kenichi SHIBATA ,  Fumihito YAMAGUCHI

    发明人： Yusaku KATSUBE ,  Junichi TAKAHASHI ,  Masaaki YAMADA ,  Toshihito HABUKA ,  Kenichi SHIBATA ,  Fumihito YAMAGUCHI

    IPC分类号： H04W88/02 ,  H03H7/01 ,  H04B1/16

    CPC分类号： H04B1/30 ,  H03H7/0153 ,  H03H11/1291 ,  H03H2210/012 ,  H03H2210/025 ,  H03H2210/036 ,  H03H2250/00

    摘要： Gain setting can be performed at high speed while reducing DC offset due to a filter cutoff frequency changeover without the need for input signal muting. A filter circuit having first and second filters is capable of allowing settings of first and second cutoff frequencies. First and second filter switch circuits and a charging circuit including a charging resistor and a charging switch are provided. For a first time period, the first switch circuit is controllably turned on while the second switch circuit is controllably turned off, thereby providing the first filter function. For a second time period, the first switch circuit is controllably turned off while the second switch circuit is controllably turned on, thereby providing the second filter function. For the first time period, the charging switch is controllably turned on so that the second capacitor is charged via the charging resistor.

    摘要翻译： 增益设置可以高速执行，同时减少由于滤波器截止频率切换引起的直流偏移，而不需要输入信号静音。 具有第一和第二滤波器的滤波器电路能够允许第一和第二截止频率的设置。 提供第一和第二滤波器开关电路以及包括充电电阻器和充电开关的充电电路。 在第一时间段中，第一开关电路被可控地导通，而第二开关电路被可控地关断，从而提供第一滤波器功能。 对于第二时间段，第一开关电路在第二开关电路被可控地接通的同时被可控制地截止，从而提供第二滤波器功能。 在第一时间段中，充电开关被可控地导通，使得第二电容器经由充电电阻器充电。