公开(公告)号：US4658356A

公开(公告)日：1987-04-14

申请号：US553235

申请日：1983-11-18

申请人： Kenichi Shiozaki ,  Makoto Kishi ,  Tomoatsu Yanagita ,  Kanji Kubo

发明人： Kenichi Shiozaki ,  Makoto Kishi ,  Tomoatsu Yanagita ,  Kanji Kubo

IPC分类号： G06F12/10 ,  G06F12/08 ,  G06F12/14 ,  G06F13/00 ,  G06F13/14

CPC分类号： G06F12/0804 ,  G06F12/1475 ,  G06F13/00

摘要： Change bits are provided in correspondence with storage information units (blocks or pages) of a storage, and indicate whether or not a "store" operation has been performed into the corresponding storage information units. The change bits are retained in a first retention device in correspondence with the storage information units, and a copy of the change bits in the first retention device is retained in a second retention device. When the store operation is performed to effect a storing of data into the storage, a control device refers to the change bit retained by the second retention device and controls updating of the change bit of the first retention device in accordance with the indication of the change bit referred to.

摘要翻译： 与存储器的存储信息单元（块或页）相对应地提供更改位，并且指示是否已经对相应的存储信息单元执行“存储”操作。 更改位与存储信息单元对应地保留在第一保持装置中，并且第一保持装置中的更改位的副本保留在第二保持装置中。 当执行存储操作以将数据存储到存储器中时，控制装置参考由第二保持装置保持的更改位，并且根据变化的指示控制第一保持装置的更改位的更新 位参考。

公开(公告)号：US4456955A

公开(公告)日：1984-06-26

申请号：US294053

申请日：1981-08-18

申请人： Tomoatsu Yanagita ,  Motonobu Nagafuji

发明人： Tomoatsu Yanagita ,  Motonobu Nagafuji

IPC分类号： G06F7/38 ,  G06F7/00 ,  G06F7/48 ,  G06F7/493 ,  G06F7/50 ,  G06F7/506 ,  G06F7/76 ,  G06F9/30 ,  G06F9/302 ,  G06F9/34 ,  G06F13/00

CPC分类号： G06F9/3001 ,  G06F7/48 ,  G06F7/49936

摘要： A data processing system has an arithmetic operating unit to process a plurality of bytes at a time and carries out an arithmetic operation on first and second operands each starting from any desired address on a main memory and having any desired number of byte length. The second operand is aligned to an operand position of the first operand and the aligned second operand is supplied to the operating unit while the first operand is supplied as it is to the operating unit. Since the second operand is aligned to the operand position of the first operand before it is processed in the operating unit, the number of times of alignment is reduced.

摘要翻译： 数据处理系统具有算术运算单元，用于一次处理多个字节，并对从主存储器上的任何所需地址开始并且具有任何期望数量的字节长度的第一和第二操作数执行算术运算。 第二操作数与第一操作数的操作数位置对齐，并且将对准的第二操作数提供给操作单元，同时将第一操作数原样提供给操作单元。 由于第二操作数在操作单元处理之前与第一操作数的操作数位置对齐，因此减少对准次数。

公开(公告)号：US5151868A

公开(公告)日：1992-09-29

申请号：US472816

申请日：1990-01-31

申请人： Yoshinori Nishiyama ,  Tomoatsu Yanagita ,  Masahiko Nagai ,  Mitsuru Morikuni ,  Kenji Matsumoto

发明人： Yoshinori Nishiyama ,  Tomoatsu Yanagita ,  Masahiko Nagai ,  Mitsuru Morikuni ,  Kenji Matsumoto

IPC分类号： H01L21/82 ,  G06F17/50 ,  H05K3/00

CPC分类号： G06F17/5077

摘要： A signal line terminal allocation method includes an electronic device which is hierarchically designed to obtain terminal allocations which satisfy electrical restrictive conditions. The electronic device includes high hierarchial components and low hierarchial components; the high hierarchial components are connected to the low hierarchical components by a plurality of signal lines through a plurality of signal line terminals. The method including the steps of: 1) obtaining all the different combinations of an allocation of the signal lines to the signal line terminals; 2) calculating a plurality of signal line lengths for all the different combinations, each of the plurality of signal line lengths corresponding to a sum of the line lengths of each of the signal lines in the allocation; and 3) selecting the combinations of allocation of signal lines in which electrical restrictions corresponding to each of the plurality of signal lines are satisfied, the electrical restrictions including the maximum line length. The above method includes groups of plural signal lines of both high and low hierarchial components.

摘要翻译： 信号线终端分配方法包括分级设计以获得满足电限制条件的终端分配的电子设备。 电子设备包括高层次组件和低层次组件; 高分层分量通过多个信号线终端通过多个信号线连接到低分层分量。 该方法包括以下步骤：1）获得信号线分配到信号线终端的所有不同组合; 2）针对所有不同的组合计算多个信号线长度，所述多个信号线长度中的每一个对应于所述分配中的每条信号线的线路长度之和; 以及3）选择其中满足对应于多条信号线中的每条信号线的电气限制的信号线分配的组合，电限制包括最大线路长度。 上述方法包括具有高和低等级分量的多个信号线的组。

公开(公告)号：US5010493A

公开(公告)日：1991-04-23

申请号：US343362

申请日：1989-04-26

申请人： Kenji Matsumoto ,  Tomoatsu Yanagita ,  Yoshinori Nishiyama ,  Masahiko Nagai ,  Mitsuru Morikuni

发明人： Kenji Matsumoto ,  Tomoatsu Yanagita ,  Yoshinori Nishiyama ,  Masahiko Nagai ,  Mitsuru Morikuni

IPC分类号： H01L21/82 ,  G06F17/50 ,  H05K3/00

CPC分类号： G06F17/5068

摘要： A load distribution method in which loads are divided into groups and each of a plurality of input pins of integrated circuits of a load is wired continuously with one stroke of a signal transmission line in a sequence from a driving output pin in each group when the wiring for distributing the drive signal from the driving output pin of an integrated circuit to plural input pins of integrated circuits, functioning as a load, is such that a plurality of intergrated circuits are mounted at given positions on a printed circuit board. In the load distribution method, the load is divided into groups by equally distributing a number of the loads so as to allow load capacities to be equal to each other on each of a plurality of signal transmission lines, and there is computed a signal propagation delay time of the signal transmission line wired equally in a distance to a load which is equal in a wiring sequence from the driving output pin in each group. Also, the loads are grouped by determining a combination of loads in which the signal propagation delay time of the signal transmission line becomes the shortest.

摘要翻译： 一种负载分配方法，其中负载被分成组，并且负载的集成电路的多个输入引脚中的每一个以每组中的驱动输出引脚的顺序从信号传输线的一行连续布线，当布线 用于将集成电路的驱动输出引脚的驱动信号分配到用作负载的集成电路的多个输入引脚，使得多个集成电路安装在印刷电路板上的给定位置。 在负载分配方法中，通过均衡地分配多个负载来将负载分成组，以便允许多个信号传输线中的每一个上的负载能力彼此相等，并且计算出信号传播延迟 信号传输线路的时间与从每个组中的驱动输出引脚的布线序列相等的负载距离相等。 此外，通过确定信号传输线的信号传播延迟时间变得最短的负载的组合来分组负载。

公开(公告)号：US4536854A

公开(公告)日：1985-08-20

申请号：US403330

申请日：1982-07-30

申请人： Tomoatsu Yanagita

发明人： Tomoatsu Yanagita

IPC分类号： G06F7/494 ,  G06F7/48 ,  G06F7/493 ,  G06F7/50 ,  G06F7/506 ,  G06F7/508 ,  G06F7/38

CPC分类号： G06F7/493 ,  G06F7/494 ,  G06F2207/3828 ,  G06F2207/4924

摘要： A decimal arithmetic unit for carrying out a decimal arithmetic operation for first and second operands each consisting of a sign digit and numeric data comprises arithmetic means for carrying out the decimal arithmetic operation and sign processing means for processing the sign digits. The numeric data excluding the sign digits of the first and second operands are supplied to the arithmetic means and the sign digits of the first and second operands are supplied to the sign processing means. An output of the arithmetic means and an output of the sign processing means are merged to produce an operation result.

摘要翻译： 用于对每个由符号数字和数字数据组成的第一和第二操作数执行十进制算术运算的十进制算术单元包括用于执行十进制运算的运算装置和用于处理符号数字的符号处理装置。 除了第一和第二操作数的符号数字之外的数字数据被提供给算术装置，并且第一和第二操作数的符号数字被提供给符号处理装置。 运算装置的输出和符号处理装置的输出被合并以产生运算结果。