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公开(公告)号：US5425099A
公开(公告)日：1995-06-13
申请号：US223647
申请日：1994-04-06
申请人： Kenji Takakura , Katsuyuki Uchida
发明人： Kenji Takakura , Katsuyuki Uchida
摘要： A positive temperature coefficient thermistor element comprising a plate-shaped ceramic body made of a ceramic material whose Curie temperature is in the range of 60.degree. to 120.degree. C., and having a thickness of 2.5 to 5.0 mm, and electrodes formed on both major surfaces of the ceramic body.
摘要翻译： 一种正温度系数热敏电阻元件，包括陶瓷材料制陶瓷体的陶瓷体，居里温度为60〜120℃，厚度为2.5〜5.0mm，电极形成于两个主体 陶瓷体的表面。
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公开(公告)号：US5315652A
公开(公告)日：1994-05-24
申请号：US850698
申请日：1992-03-11
申请人： Kenji Takakura , Katsuyuki Uchida
发明人： Kenji Takakura , Katsuyuki Uchida
摘要： A terminal for telegraph and telephone systems using as an overvoltage/overcurrent protecting component a positive temperature coefficient thermistor element comprising a plate-shaped ceramic body made of a ceramic material whose Curie temperature is in the range of 60.degree. to 120.degree. C., and having a thickness of 2.5 to 5.0 mm, and electrodes formed on both major surfaces of the ceramic body.
摘要翻译： 一种用作过电压/过电流保护元件的电报和电话系统的端子，正温度系数热敏电阻元件包括由居里温度在60至120℃范围内的陶瓷材料制成的板状陶瓷体，以及 厚度为2.5〜5.0mm，电极形成在陶瓷体的两个主面上。
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3.发明授权
公开(公告)号：US5686830A
公开(公告)日：1997-11-11
申请号：US658683
申请日：1996-06-05
申请人： Kenji Takakura , Yuichi Takaoka
发明人： Kenji Takakura , Yuichi Takaoka
摘要： A method of supplying positive temperature coefficient thermistor elements in which a plurality of positive temperature coefficient thermistor elements 1 are divided into groups G.sub.1 to G.sub.8 for each range of predetermined resistance values, two arbitrary positive temperature coefficient thermistor elements are taken out of one of the groups G.sub.1 to G.sub.8 and supplied as one set of positive temperature coefficient thermistor elements.
摘要翻译： 对于每个预定电阻值的范围，提供正温度系数热敏电阻元件的方法，其中多个正温度系数热敏电阻元件1被分成组G1至G8，两个任意正温度系数热敏电阻元件从组中的一个中取出 G1至G8并作为一组正温度系数热敏电阻元件提供。
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公开(公告)号：US20090212387A1
公开(公告)日：2009-08-27
申请号：US12359635
申请日：2009-01-26
申请人： Yasuhiro Ito , Kunihiro Miyazaki , Kenji Takakura
发明人： Yasuhiro Ito , Kunihiro Miyazaki , Kenji Takakura
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/78
摘要： A trench is formed on a semiconductor substrate with a first insulation film patterned on the semiconductor substrate as a mask; a second insulation film is embedded in the trench and flattened; an upper portion of the first insulation film is selectively removed, and a part of a side face of the second insulation film is exposed; a part of the second insulation film is isotropically removed; a lower portion of the remaining first insulation film is selectively removed; and then a part of the remaining second insulation film is further isotropically removed so that an upper face of the second insulation film is at a predetermined height from a surface of the semiconductor substrate, a taper having a minimum taper angle of 90° or more is formed on the side face of the second insulation film, and a STI is formed.
摘要翻译： 在半导体衬底上形成有在半导体衬底上形成图案的第一绝缘膜作为掩模的沟槽; 将第二绝缘膜嵌入沟槽并平坦化; 选择性地去除第一绝缘膜的上部，暴露第二绝缘膜的侧面的一部分; 第二绝缘膜的一部分被各向同性地去除; 选择性地去除剩余的第一绝缘膜的下部; 然后将剩余的第二绝缘膜的一部分进一步各向同性地去除，使得第二绝缘膜的上表面距离半导体衬底的表面处于预定高度，具有最小锥角为90°或更大的锥形为 形成在第二绝缘膜的侧面上，并且形成STI。
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5.发明申请公开(公告)号：US20110089525A1
公开(公告)日：2011-04-21
申请号：US12926905
申请日：2010-12-16
申请人： Yasuhiro Ito , Kunihiro Miyazaki , Kenji Takakura
发明人： Yasuhiro Ito , Kunihiro Miyazaki , Kenji Takakura
IPC分类号： H01L29/06
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/78
摘要： A trench is formed on a semiconductor substrate with a first insulation film patterned on the semiconductor substrate as a mask; a second insulation film is embedded in the trench and flattened; an upper portion of the first insulation film is selectively removed, and a part of a side face of the second insulation film is exposed; a part of the second insulation film is isotropically removed; a lower portion of the remaining first insulation film is selectively removed; and then a part of the remaining second insulation film is further isotropically removed so that an upper face of the second insulation film is at a predetermined height from a surface of the semiconductor substrate, a taper having a minimum taper angle of 90° or more is formed on the side face of the second insulation film, and a STI is formed.
摘要翻译： 在半导体衬底上形成有在半导体衬底上形成图案的第一绝缘膜作为掩模的沟槽; 将第二绝缘膜嵌入沟槽并平坦化; 选择性地去除第一绝缘膜的上部，暴露第二绝缘膜的侧面的一部分; 第二绝缘膜的一部分被各向同性地去除; 选择性地去除剩余的第一绝缘膜的下部; 然后将剩余的第二绝缘膜的一部分进一步各向同性地去除，使得第二绝缘膜的上表面距离半导体衬底的表面处于预定高度，具有最小锥角为90°或更大的锥形为 形成在第二绝缘膜的侧面上，并且形成STI。
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公开(公告)号：US07875527B2
公开(公告)日：2011-01-25
申请号：US12359635
申请日：2009-01-26
申请人： Yasuhiro Ito , Kunihiro Miyazaki , Kenji Takakura
发明人： Yasuhiro Ito , Kunihiro Miyazaki , Kenji Takakura
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/78
摘要： A trench is formed on a semiconductor substrate with a first insulation film patterned on the semiconductor substrate as a mask; a second insulation film is embedded in the trench and flattened; an upper portion of the first insulation film is selectively removed, and a part of a side face of the second insulation film is exposed; a part of the second insulation film is isotropically removed; a lower portion of the remaining first insulation film is selectively removed; and then a part of the remaining second insulation film is further isotropically removed so that an upper face of the second insulation film is at a predetermined height from a surface of the semiconductor substrate, a taper having a minimum taper angle of 90° or more is formed on the side face of the second insulation film, and a STI is formed.
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