公开(公告)号：US06271691B1

公开(公告)日：2001-08-07

申请号：US09605887

申请日：2000-06-29

申请人： Kenji Toyoda ,  Kimio Maruyama ,  Eisuke Inoue

发明人： Kenji Toyoda ,  Kimio Maruyama ,  Eisuke Inoue

IPC分类号： H03K522

CPC分类号： H03F3/393 ,  H03K5/249

摘要： A chopper type voltage comparison circuit is disclosed which restrain leakage current between an input and output nodes of each amplifying circuit to enable normal voltage comparisons even if a threshold voltage for each transistor is reduced to diminish a power supply voltage. This chopper type voltage comparison circuit comprises a capacitor C1 having an input voltage or a reference voltage selectively supplied to one end thereof depending on whether a voltage input operation or a voltage comparison operation is to be performed, a CMOS clocked inverter circuit CINV1 for voltage amplification having a voltage at the other end of the capacitor input to an input node thereof and having a clock gate section biased so as to be constantly conductive, and a CMOS clocked inverter circuit CINV4 for input voltage setting having the same circuit configuration as the CMOS clocked inverter circuit for voltage amplification, having an input and output nodes short-circuited thereto, and connected to the input node of the CMOS clocked inverter circuit for voltage amplification so that the clock gate section is switch-controlled to be turned on for the voltage input operation, while the clock gate section is switch-controlled to be turned off for the voltage comparison operation.

摘要翻译： 公开了一种斩波型电压比较电路，其抑制每个放大电路的输入和输出节点之间的漏电流，以便即使降低每个晶体管的阈值电压以减小电源电压，也能进行正常电压比较。 该斩波型电压比较电路包括：电容器C1，其具有根据是否要执行电压输入操作或电压比较操作选择性地提供给其一端的输入电压或参考电压;用于电压放大的CMOS时钟反相器电路CINV1 在输入到其输入节点的电容器的另一端处具有电压，并且具有偏置以恒定导通的时钟门极部分;以及具有与CMOS时钟相同的电路配置的输入电压设置的CMOS时钟反相器电路CINV4 用于电压放大的逆变器电路，具有与其短路的输入和输出节点，并连接到CMOS时钟反相器电路的输入节点用于电压放大，使得时钟门极部分被开关控制为导通，用于电压输入 操作时，而对于电压比较运算，时钟门极段被开关控制为截止 ation。

公开(公告)号：US07123527B2

公开(公告)日：2006-10-17

申请号：US10803936

申请日：2004-03-19

申请人： Naokazu Kuzuno ,  Kiyoharu Oikawa ,  Kimio Maruyama ,  Yasuhiro Watanabe ,  Masaya Kubota

发明人： Naokazu Kuzuno ,  Kiyoharu Oikawa ,  Kimio Maruyama ,  Yasuhiro Watanabe ,  Masaya Kubota

IPC分类号： G11C7/00

CPC分类号： G11C29/24 ,  G11C29/02 ,  G11C29/027 ,  G11C29/78

摘要： A redundancy fuse circuit including a function of replacing a defective cell in a memory cell array with a redundancy cell, comprising a fuse circuit in which an address of the defective cell or a block including the defective cell is programmed as a defective address by presence/absence of cut-off of a fuse, a data latch circuit which latches a signal supplied from a tester to program the defective address in a dummy manner, and a comparator which replaces the defective cell with the redundancy cell based on an address signal supplied from the tester and an output signal of the data latch circuit at an operation confirmation time of the redundancy fuse circuit.

摘要翻译： 一种冗余熔丝电路，包括用冗余单元替换存储单元阵列中的有缺陷单元的功能，包括熔丝电路，其中有缺陷单元的地址或包括有缺陷单元的块被编程为有缺陷地址， 不存在保险丝的截止，锁存从测试器提供的信号以虚拟方式对缺陷地址进行编程的数据锁存电路，以及基于从冗余单元提供的地址信号替换缺陷单元的比较器 测试器和数据锁存电路的输出信号在冗余熔丝电路的操作确认时间。

公开(公告)号：US06643203B2

公开(公告)日：2003-11-04

申请号：US10230229

申请日：2002-08-29

申请人： Kiyoharu Oikawa ,  Kimio Maruyama ,  Yasuhiro Watanabe ,  Naokazu Kuzuno

发明人： Kiyoharu Oikawa ,  Kimio Maruyama ,  Yasuhiro Watanabe ,  Naokazu Kuzuno

IPC分类号： G11C702

CPC分类号： G11C29/025 ,  G11C7/06 ,  G11C16/28 ,  G11C29/02 ,  G11C2207/005

摘要： A semiconductor memory device includes a memory cell array, a read control circuit, a row decoder, a column decoder, a sense amplifier, and a sense amplifier control circuit. The read control circuit produces a precharge signal to precharge a bit line of the memory cell array. The sense amplifier amplifies data read onto the bit line. In reading data from a memory cell, the sense amplifier control circuit enables the sense amplifier and inhibits entry of read data from a memory cell into the sense amplifier only for a fixed interval after a fixed time after the precharging signal has been negated. The sense amplifier control circuit allows entry of read data into the sense amplifier while the sense amplifier is being disabled.

公开(公告)号：US07260012B2

公开(公告)日：2007-08-21

申请号：US10777971

申请日：2004-02-13

申请人： Naokazu Kuzuno ,  Kimio Maruyama ,  Yasuhiro Hegi ,  Kiyoharu Oikawa

发明人： Naokazu Kuzuno ,  Kimio Maruyama ,  Yasuhiro Hegi ,  Kiyoharu Oikawa

IPC分类号： G11C17/18

CPC分类号： G11C17/18

摘要： One end of a fuse is connected to a ground point via a transistor N1A, and the other end thereof is connected to a node VaA. For example, at a fuse connection case, when INTV=“H” is input to the gate of the transistor N1A, the node VaA becomes “L.” At INTV=“L”, a transistor P1A having a low “on” resistance turns ON, and the node VaA is quickly precharged. At INTV=“H”, the transistor N1A turns ON, and the node VaA is quickly discharged.

摘要翻译： 保险丝的一端通过晶体管N1A连接到接地点，另一端连接到节点VaA。 例如，在熔丝连接情况下，当INTV =“H”被输入到晶体管N1A的栅极时，节点VaA变为“L”。 在INTV =“L”时，具有低“导通”电阻的晶体管P1A导通，并且节点VaA被快速预充电。 在INTV =“H”时，晶体管N 1A导通，节点VaA快速放电。

公开(公告)号：US4523500A

公开(公告)日：1985-06-18

申请号：US484991

申请日：1983-04-14

申请人： Kimio Maruyama

发明人： Kimio Maruyama

IPC分类号： B21D13/04 ,  B23D25/04 ,  B26D1/56

CPC分类号： B23D25/04 ,  B21D13/04 ,  B21D53/025 ,  Y10T83/0515 ,  Y10T83/343 ,  Y10T83/4659 ,  Y10T83/4664 ,  Y10T83/4763 ,  Y10T83/53 ,  Y10T83/6472

摘要： A method and apparatus for cutting a continuous corrugated member while conveying it in a longitudinal direction thereof, in which a movable cutter blade is moved forward in the same direction as the conveying direction of the corrugated member at the same speed as the conveying speed of the corrugated member. The cutter blade is also reciprocated to cut the corrugated member when the cutter blade is moved forward.

摘要翻译： 一种用于在沿着其纵向方向输送连续波纹状构件的同时切割连续的波纹状构件的方法和装置，其中可动切割刀片以与波纹构件的输送方向相同的方向向前移动， 瓦楞纸板。 当切割刀片向前移动时，切割刀片也往复运动以切割波纹部件。

公开(公告)号：US07243199B2

公开(公告)日：2007-07-10

申请号：US10609563

申请日：2003-07-01

申请人： Kiyoharu Oikawa ,  Kimio Maruyama ,  Yasuhiro Watanabe ,  Naokazu Kuzuno ,  Masaya Kubota

发明人： Kiyoharu Oikawa ,  Kimio Maruyama ,  Yasuhiro Watanabe ,  Naokazu Kuzuno ,  Masaya Kubota

IPC分类号： G06F12/14

CPC分类号： G06F21/79 ,  G06F12/1433

摘要： A memory data protection system is disclosed, which comprises a memory circuit, a protection contents indicating section which stores a security bit and a protection bit, a protection function circuit which determines permission/prohibition of reading of data from the memory circuit and permission/prohibition of writing of data to the memory circuit in accordance with the security bit and the protection bit, and a protection function locking/unlocking circuit which makes the protection function circuit in a lock state to forcibly prohibit reading of data from the memory circuit and writing of data into the memory circuit in a time period from when a power supply is turned on till when the protection function circuit completes reading of the security bit and the protection bit from the protection contents indicating section into data buses, and after lapse of the time period, the protection function locking/unlocking circuit unlocks the lock state.

摘要翻译： 公开了一种存储器数据保护系统，其包括存储器电路，存储安全位和保护位的保护内容指示部分，确定从存储器电路读取数据的许可/禁止和允许/禁止的保护功能电路 根据安全位和保护位将数据写入存储器电路，以及保护功能锁定/解锁电路，其使保护功能电路处于锁定状态，以强制禁止从存储器电路读取数据和写入 在从电源接通开始直到保护功能电路完成从保护内容指示部分读取安全位和保护位到数据总线的时间段内的数据到存储器电路中，并且在经过时间段之后 ，保护功能锁定/解锁电路解锁锁定状态。