Multi-run selective pattern and etch wafer process
    1.
    发明授权
    Multi-run selective pattern and etch wafer process 失效
    多运行选择性图案和蚀刻晶圆工艺

    公开(公告)号:US07060626B2

    公开(公告)日:2006-06-13

    申请号:US10604087

    申请日:2003-06-25

    IPC分类号: H01L21/302

    摘要: A method for forming a semiconductor wafer comprising of applying a first patterned resist to at least one first predetermined region of a wafer where said at least one first predetermined region of said wafer are protected by said first patterned resist and a first remaining portion of said wafer is not protected by said first patterned resist; etching said first remaining portion of said wafer not protected by said first pattern resist; stripping the first pattern resist from said wafer; applying a second patterned resist to at least one second pre-determined region of said wafer where said at least one second predetermined region of said wafer are protected by a second patterned resist and a second remaining portion is not protected by said second patterned resist; etching said second remaining portion not protected by said second patterned resist; and stripping said second patterned resist from said wafer.

    摘要翻译: 一种用于形成半导体晶片的方法,包括将第一图案化抗蚀剂施加到晶片的至少一个第一预定区域,其中所述晶片的所述至少一个第一预定区域被所述第一图案化抗蚀剂保护并且所述晶片的第一剩余部分 不受所述第一图案化抗蚀剂的保护; 蚀刻所述晶片的未被所述第一图案抗蚀剂保护的所述第一剩余部分; 从所述晶片剥离第一图案抗蚀剂; 将第二图案化抗蚀剂施加到所述晶片的至少一个第二预定区域,其中所述晶片的所述至少一个第二预定区域被第二图案化抗蚀剂保护,并且第二剩余部分不被所述第二图案化抗蚀剂保护; 蚀刻不被所述第二图案化抗蚀剂保护的所述第二剩余部分; 以及从所述晶片剥离所述第二图案化抗蚀剂。