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公开(公告)号：US07087997B2
公开(公告)日：2006-08-08
申请号：US09805027
申请日：2001-03-12
申请人： Lloyd G. Burrell , Edward E. Cooney, III , Jeffrey P. Gambino , John E. Heidenreich, III , Hyun Koo Lee , Mark D. Levy , Baozhen Li , Stephen E. Luce , Thomas L. McDevitt , Anthony K. Stamper , Kwong Hon Wong , Sally J. Yankee
发明人： Lloyd G. Burrell , Edward E. Cooney, III , Jeffrey P. Gambino , John E. Heidenreich, III , Hyun Koo Lee , Mark D. Levy , Baozhen Li , Stephen E. Luce , Thomas L. McDevitt , Anthony K. Stamper , Kwong Hon Wong , Sally J. Yankee
CPC分类号： H01L21/76843 , H01L21/76838 , H01L23/5226 , H01L23/53223 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.
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公开(公告)号：US20130256826A1
公开(公告)日：2013-10-03
申请号：US13437273
申请日：2012-04-02
IPC分类号： H01L29/06
CPC分类号： H01L29/0619 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip comprising a guard ring formed on a semiconductor substrate that surrounds the active region of the integrated circuit chip and extends from the semiconductor substrate through one or more of a plurality of wiring levels. The guard ring comprises stacked metal lines with spaces breaking up each respective metal line. Each space may be formed such that it partially overlies the space in the metal line directly below but does not overlie any other space. Alternatively, each space may also be formed such that each space is at least completely overlying the space in the metal line below it.
摘要翻译： 一种集成电路芯片，包括形成在半导体衬底上的保护环，所述保护环围绕所述集成电路芯片的有源区并且从所述半导体衬底延伸通过多个布线层中的一个或多个。 保护环包括堆叠金属线，空间分开各个金属线。 每个空间可以被形成为使得其部分地覆盖金属线中的空间直接在下方，但不覆盖任何其它空间。 或者，每个空间也可以形成为使得每个空间至少完全覆盖在其下面的金属线中的空间。
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公开(公告)号：US20130026587A1
公开(公告)日：2013-01-31
申请号：US13189961
申请日：2011-07-25
CPC分类号： H01L27/14623 , H01L27/14636 , H01L27/14687
摘要： Pixel sensor cells with an opaque mask layer and methods of manufacturing are provided. The method includes forming a transparent layer over at least one active pixel and at least one dark pixel of a pixel sensor cell. The method further includes forming an opaque region in the transparent layer over the at least one dark pixel.
摘要翻译： 提供了具有不透明掩模层的像素传感器单元和制造方法。 该方法包括在像素传感器单元的至少一个有源像素和至少一个暗像素的上方形成透明层。 该方法还包括在至少一个暗像素上的透明层中形成不透明区域。
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4.发明授权公开(公告)号：US07823106B2
公开(公告)日：2010-10-26
申请号：US12045984
申请日：2008-03-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method, computer system and program product introduce adding a variable performance ranking parameter to a diagram of a circuit to drive implementation of modifications that are yield improving, performance boosting, or performance-neutral. The information is paired to accomplish a more complete design for manufacturability modification in the design of circuits implemented on chips. In this matter, both yield and chip performance are improved.
摘要翻译： 一种方法，计算机系统和程序产品引入了将可变性能排名参数添加到电路图中，以驱动实现改进的效果，提高效率，提升性能或性能中立。 该信息配对，以便在芯片上实现的电路设计中完成更完整的可制造性修改设计。 在这个问题上，产量和芯片性能均有所提高。
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5.发明申请公开(公告)号：US20090235214A1
公开(公告)日：2009-09-17
申请号：US12045984
申请日：2008-03-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method, computer system and program product introduce adding a variable performance ranking parameter to a diagram of a circuit to drive implementation of modifications that are yield improving, performance boosting, or performance-neutral. The information is paired to accomplish a more complete design for manufacturability modification in the design of circuits implemented on chips. In this matter, both yield and chip performance are improved.
摘要翻译： 一种方法，计算机系统和程序产品引入了将可变性能排名参数添加到电路图中，以驱动实现改进的效果，提高效率，提升性能或性能中立。 该信息配对，以便在芯片上实现的电路设计中完成更完整的可制造性修改设计。 在这个问题上，产量和芯片性能均有所提高。
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公开(公告)号：US07037824B2
公开(公告)日：2006-05-02
申请号：US10844533
申请日：2004-05-13
申请人： Lloyd G. Burrell , Edward E. Cooney, III , Jeffrey P. Gambino , John E. Heidenreich, III , Hyun Koo Lee , Mark D. Levy , Baozhen Li , Stephen E. Luce , Thomas L. McDevitt , Anthony K. Stamper , Kwong Hon Wong , Sally J. Yankee
发明人： Lloyd G. Burrell , Edward E. Cooney, III , Jeffrey P. Gambino , John E. Heidenreich, III , Hyun Koo Lee , Mark D. Levy , Baozhen Li , Stephen E. Luce , Thomas L. McDevitt , Anthony K. Stamper , Kwong Hon Wong , Sally J. Yankee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76838 , H01L23/5226 , H01L23/53223 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.
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公开(公告)号：US08729664B2
公开(公告)日：2014-05-20
申请号：US13437273
申请日：2012-04-02
IPC分类号： H01L29/15 , H01L23/52 , H01L29/47 , H01L27/095
CPC分类号： H01L29/0619 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip comprising a guard ring formed on a semiconductor substrate that surrounds the active region of the integrated circuit chip and extends from the semiconductor substrate through one or more of a plurality of wiring levels. The guard ring comprises stacked metal lines with spaces breaking up each respective metal line. Each space may be formed such that it partially overlies the space in the metal line directly below but does not overlie any other space. Alternatively, each space may also be formed such that each space is at least completely overlying the space in the metal line below it.
摘要翻译： 一种集成电路芯片，包括形成在半导体衬底上的保护环，所述保护环围绕所述集成电路芯片的有源区并从所述半导体衬底延伸穿过多个布线层中的一个或多个。 保护环包括堆叠金属线，空间分开各个金属线。 每个空间可以被形成为使得其部分地覆盖金属线中的空间直接在下方，但不覆盖任何其它空间。 或者，每个空间也可以形成为使得每个空间至少完全覆盖在其下面的金属线中的空间。
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公开(公告)号：US07060626B2
公开(公告)日：2006-06-13
申请号：US10604087
申请日：2003-06-25
申请人： Kenneth A. Bandy , Vincent J. Carlos , Mark D. Levy , Sara L. Lucas , Timothy C. Milmore , Matthew C. Nicholls , Jason Nowakowski
发明人： Kenneth A. Bandy , Vincent J. Carlos , Mark D. Levy , Sara L. Lucas , Timothy C. Milmore , Matthew C. Nicholls , Jason Nowakowski
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0271 , H01L21/31144
摘要： A method for forming a semiconductor wafer comprising of applying a first patterned resist to at least one first predetermined region of a wafer where said at least one first predetermined region of said wafer are protected by said first patterned resist and a first remaining portion of said wafer is not protected by said first patterned resist; etching said first remaining portion of said wafer not protected by said first pattern resist; stripping the first pattern resist from said wafer; applying a second patterned resist to at least one second pre-determined region of said wafer where said at least one second predetermined region of said wafer are protected by a second patterned resist and a second remaining portion is not protected by said second patterned resist; etching said second remaining portion not protected by said second patterned resist; and stripping said second patterned resist from said wafer.
摘要翻译： 一种用于形成半导体晶片的方法，包括将第一图案化抗蚀剂施加到晶片的至少一个第一预定区域，其中所述晶片的所述至少一个第一预定区域被所述第一图案化抗蚀剂保护并且所述晶片的第一剩余部分 不受所述第一图案化抗蚀剂的保护; 蚀刻所述晶片的未被所述第一图案抗蚀剂保护的所述第一剩余部分; 从所述晶片剥离第一图案抗蚀剂; 将第二图案化抗蚀剂施加到所述晶片的至少一个第二预定区域，其中所述晶片的所述至少一个第二预定区域被第二图案化抗蚀剂保护，并且第二剩余部分不被所述第二图案化抗蚀剂保护; 蚀刻不被所述第二图案化抗蚀剂保护的所述第二剩余部分; 以及从所述晶片剥离所述第二图案化抗蚀剂。
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公开(公告)号：US08592244B2
公开(公告)日：2013-11-26
申请号：US13189961
申请日：2011-07-25
IPC分类号： H01L21/00
CPC分类号： H01L27/14623 , H01L27/14636 , H01L27/14687
摘要： Pixel sensor cells with an opaque mask layer and methods of manufacturing are provided. The method includes forming a transparent layer over at least one active pixel and at least one dark pixel of a pixel sensor cell. The method further includes forming an opaque region in the transparent layer over the at least one dark pixel.
摘要翻译： 提供了具有不透明掩模层的像素传感器单元和制造方法。 该方法包括在像素传感器单元的至少一个有源像素和至少一个暗像素的上方形成透明层。 该方法还包括在至少一个暗像素上的透明层中形成不透明区域。
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