公开(公告)号：US06768352B1

公开(公告)日：2004-07-27

申请号：US10293392

申请日：2002-11-13

申请人： Kenneth A. Maher ,  Anthony Blake

发明人： Kenneth A. Maher ,  Anthony Blake

IPC分类号： H03K300

CPC分类号： H04L25/0292 ,  H04L25/0276 ,  H04L25/028

摘要： An improved communication system, receiver, and method are provided that can reduce input voltages received by the receiver whenever those voltages extend upward to the maximum common-mode voltage range. A detect circuit determines whether the input voltages are at or near the maximum range. If so, the detect circuit sends a control signal to a level shift circuit which will reduce the input voltages by a predefined amount. The reduced voltages can then be forwarded to a sense circuit which preferably operates at a power supply voltage that is less than the maximum differential input voltage (i.e., the maximum voltage on the differential pair of signals), or less than the maximum common-mode voltage of the differential input signals. The sense circuit can thereby operate at a relatively wide common-mode voltage range, and utilizes a lower power supply voltage. The sense circuit can also be made up of a relatively simple differential pair of transistors with corresponding resistor loads in order to sense a differential input voltage range of, for example, 800 millivolts to 2.4 volts prior to voltage reduction, and 800 millivolts to 2.0 volts after voltage reduction.

摘要翻译： 提供了一种改进的通信系统，接收机和方法，其可以在每当这些电压向上延伸到最大共模电压范围时减小接收机接收的输入电压。 检测电路确定输入电压是否处于或接近最大范围。 如果是这样，则检测电路将控制信号发送到电平移位电路，该电平移位电路将输入电压减小预定量。 然后，降低的电压可以被转发到感测电路，其优选地在小于最大差分输入电压（即差分信号对上的最大电压）的电源电压下操作，或者小于最大共模 差分输入信号的电压。 因此，感测电路可以在相对较宽的共模电压范围内工作，并且利用较低的电源电压。 感测电路还可以由具有相应电阻器负载的相对简单的差分对晶体管组成，以便在电压降低之前感测例如800毫伏至2.4伏的差分输入电压范围，以及800毫伏至2.0伏特 电压降低后。

公开(公告)号：US06404682B1

公开(公告)日：2002-06-11

申请号：US09876981

申请日：2001-06-08

申请人： James W. Lutley ,  Neil P. Raftery ,  Jonathan F. Churchill ,  Kenneth A. Maher

发明人： James W. Lutley ,  Neil P. Raftery ,  Jonathan F. Churchill ,  Kenneth A. Maher

IPC分类号： G11C700

CPC分类号： G11C8/00

摘要： An apparatus comprising a first register, a second register and a plurality of compare circuits. The first register may be configured to store a plurality of first address bits. The second register may be configured to store a plurality of second address bits. The plurality of compare circuits may each be configured to generate an output signal in response to one of said plurality of first address bits and one of said plurality of second address bits. The output signals are generally each at either (i) the same logic state or (ii), a don't care state.

摘要翻译： 一种装置，包括第一寄存器，第二寄存器和多个比较电路。 第一寄存器可以被配置为存储多个第一地址位。 第二寄存器可以被配置为存储多个第二地址位。 多个比较电路可以各自被配置为响应于所述多个第一地址位之一和所述多个第二地址位之一而产生输出信号。 输出信号通常分别为（i）相同的逻辑状态或（ii），无关状态。

公开(公告)号：US06288948B1

公开(公告)日：2001-09-11

申请号：US09539903

申请日：2000-03-31

申请人： James W. Lutley ,  Neil P. Raftery ,  Jonathan F. Churchill ,  Kenneth A. Maher

发明人： James W. Lutley ,  Neil P. Raftery ,  Jonathan F. Churchill ,  Kenneth A. Maher

IPC分类号： G11C800

CPC分类号： G11C8/00

摘要： An apparatus comprising a first register, a second register and a plurality of compare circuits. The first register may be configured to store a plurality of first address bits. The second register may be configured to store a plurality of second address bits. The plurality of compare circuits may each be configured to generate an output signal in response to one of said plurality of first address bits and one of said plurality of second address bits. The output signals are generally each at either (i) the same logic state or (ii) a high-Z state.

摘要翻译： 一种装置，包括第一寄存器，第二寄存器和多个比较电路。 第一寄存器可以被配置为存储多个第一地址位。 第二寄存器可以被配置为存储多个第二地址位。 多个比较电路可以各自被配置为响应于所述多个第一地址位之一和所述多个第二地址位中的一个而产生输出信号。 输出信号通常各自处于（i）相同的逻辑状态或（ii）高Z状态。