公开(公告)号：US5574814A

公开(公告)日：1996-11-12

申请号：US381168

申请日：1995-01-31

申请人： Kenneth C. Noddings ,  Robert C. Gardner ,  Thomas J. Hirsch ,  Charles L. Spooner ,  Michael A. Olla ,  Jason J. Yu

发明人： Kenneth C. Noddings ,  Robert C. Gardner ,  Thomas J. Hirsch ,  Charles L. Spooner ,  Michael A. Olla ,  Jason J. Yu

IPC分类号： G02B6/42 ,  G02B6/36

CPC分类号： G02B6/4231 ,  G02B6/4249

摘要： An assembly of an optical interconnect module adaptable for mating with an optical connector having at least one optical fiber and an alignment pin. A method of assembly includes the steps of (1) mounting an optical device onto a connector body, wherein the connector body is a portion of the optical interconnect module, and wherein the optical device is operable for transmitting or receiving optical signals to/from the optical fiber, (2) inputting a relative position between the alignment pin and an end of the optical fiber, (3) and forming a slot in the connector body by using the measured relative position between the alignment pin and the end of the optical fiber, wherein a relative position between the slot and the optical transceiver mirrors the relative position between the alignment pin and the end of the optical fiber so that the optical device and the end of the optical fiber are substantially aligned to permit transmission of the optical signals when the optical connector and the optical interconnect module are mated, wherein the slot is adaptable for receiving the alignment pin.

摘要翻译： 光学互连模块的组件，其适于与具有至少一个光纤和对准销的光学连接器配合。 一种组装方法包括以下步骤：（1）将光学装置安装到连接器主体上，其中连接器主体是光互连模块的一部分，并且其中光学装置可操作用于向/从 光纤，（2）在对准销和光纤端部之间输入相对位置，（3）并且通过使用测量的对准销与光纤端部之间的相对位置在连接器主体中形成槽 ，其中所述槽和所述光收发器之间的相对位置反映所述对准引脚和所述光纤端部之间的相对位置，使得所述光学器件和所述光纤的端部基本上对准以允许所述光信号的传输， 光学连接器和光学互连模块配合，其中槽适于接收对准销。

公开(公告)号：US07256652B1

公开(公告)日：2007-08-14

申请号：US11221643

申请日：2005-09-08

申请人： Emerson S. Fang ,  Thomas J. Hirsch

发明人： Emerson S. Fang ,  Thomas J. Hirsch

IPC分类号： H03F3/45

CPC分类号： H03F3/45188 ,  H03F1/52 ,  H03F1/523 ,  H03F2200/321 ,  H03F2203/45052 ,  H03F2203/45322

摘要： A differential receiver circuit. In one embodiment, the circuit includes first and second input transistors, each having a first terminal coupled to a bias node (a first and second bias node, respectively), as well as first and second bias transistors, each having a first terminal coupled to the first and second bias nodes, respectively. The circuit further includes a first current source coupled to provide current to the first bias node and a second current source coupled to the second bias node. The differential receiver circuit is coupled to first and second, which receive first and second voltages, respectively. The first and second current sources provide current to the first and second bias nodes, respectively, such that the voltage present on the first and second bias nodes remains with approximately a threshold voltage of a midpoint between the voltages present on the first and second voltage nodes.

摘要翻译： 差分接收电路。 在一个实施例中，电路包括第一和第二输入晶体管，每个具有耦合到偏置节点（分别为第一和第二偏置节点）的第一端子以及第一和第二偏置晶体管，每个偏置晶体管具有耦合到 第一和第二偏置节点。 电路还包括耦合以向第一偏置节点提供电流的第一电流源和耦合到第二偏置节点的第二电流源。 差分接收器电路分别接收第一和第二电压，第一和第二电压分别接收第一和第二电压。 第一和第二电流源分别向第一和第二偏置节点提供电流，使得存在于第一和第二偏置节点上的电压保持在第一和第二电压节点上存在的电压之间的中点的大约阈值电压 。

公开(公告)号：US06496383B1

公开(公告)日：2002-12-17

申请号：US09635332

申请日：2000-08-09

申请人： Dennis J. Herrell ,  Thomas J. Hirsch

发明人： Dennis J. Herrell ,  Thomas J. Hirsch

IPC分类号： H05K710

CPC分类号： H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In an integrated circuit carrier having a large number of power pins allocated to an internal power plane, the current flowing through the power pins may divide very unevenly, and result in current flow through some of the power pins which exceeds the maximum specification for either the package pin or for the socket into which the package may be inserted. In such a package, the magnitude of the current flowing through the highest current power pin may be reduced by configuring the resistance of the power plane(s) and vias to provide approximately the same total resistance to every power pin location. Slots may be cut in a package power plane to alter the current path and raise the impedance of the conduction path between some of the package power pins and the internal contact pads otherwise having the lowest impedance. If the package, such as a pin-grid-array package, includes more than one row of pins along an edge of the package, the internal package vias may be arranged to provide an impedance from die footprint to the outer row of pins which is not substantially higher than that of the inner row of pins. In this fashion the aggregate current carrying capacity of the carrier may be increased by reducing the difference in current flow between power pins having the highest current flow and power pins having the lowest current flow. The current flow through all the power pins may then be operated nearer to the design maximum of the particular connector used, or the design maximum of the carrier itself.

摘要翻译： 在具有分配给内部电力平面的大量电源引脚的集成电路载体中，流过电源引脚的电流可能非常不均匀地分配，并且导致电流流过一些超过最大规格的电源引脚 包装销或用于可以插入包装的插座。 在这种封装中，流过最高电流电源引脚的电流的​​大小可以通过配置电源平面和通孔的电阻来减小，以提供与每个电源引脚位置大致相同的总电阻。 插槽可以在封装电源平面中切割以改变电流路径并且提高一些封装电源引脚和内部接触焊盘之间的导通路径的阻抗，否则具有最低阻抗。 如果诸如针阵列阵列封装的封装在封装的边缘处包括多于一行的引脚，则内部封装通孔可以被布置成提供从管芯封装到外部引脚排的阻抗， 基本上不比内销销的高。 以这种方式，可以通过减小具有最高电流的电源引脚和具有最低电流的电源引脚之间的电流差异来增加载体的总电流承载能力。 然后，可以使所有电源引脚的电流流动更接近所使用的特定连接器的设计最大值，或者载体本身的设计最大值。