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1.发明授权Prioritized design for manufacturing virtualization with design rule checking filtering 有权用设计规则检查过滤制造虚拟化的优先设计公开(公告)号：US09026970B2
公开(公告)日：2015-05-05
申请号：US13788046
申请日：2013-03-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An approach is provided to generate a number of virtualized circuit designs by applying design-for-manufacturing (DFM) processes to a circuit design. The virtualized circuit designs are checked using design rule checks (DRCs), with the checking resulting in a design rule error quantity that corresponds to each of the virtualized circuit designs. One of the virtualized circuit designs is selected for use in manufacturing the circuit design with the selection based each of the design's design rule error quantities.
摘要翻译： 提供了一种通过将设计制造（DFM）处理应用于电路设计来生成多个虚拟化电路设计的方法。 使用设计规则检查（DRC）检查虚拟化电路设计，检查导致与每个虚拟化电路设计相对应的设计规则错误量。 选择虚拟化电路设计中的一个用于制造电路设计，其中基于每个设计规则误差量进行选择。
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2.发明申请Prioritized Design for Manufacturing Virtualization with Design Rule Checking Filtering 有权用设计规则检查过滤制造虚拟化的优先设计公开(公告)号：US20140258951A1
公开(公告)日：2014-09-11
申请号：US13788046
申请日：2013-03-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An approach is provided to generate a number of virtualized circuit designs by applying design-for-manufacturing (DFM) processes to a circuit design. The virtualized circuit designs are checked using design rule checks (DRCs), with the checking resulting in a design rule error quantity that corresponds to each of the virtualized circuit designs. One of the virtualized circuit designs is selected for use in manufacturing the circuit design with the selection based each of the design's design rule error quantities.
摘要翻译： 提供了一种通过将设计制造（DFM）处理应用于电路设计来生成多个虚拟化电路设计的方法。 使用设计规则检查（DRC）检查虚拟化电路设计，检查导致与每个虚拟化电路设计相对应的设计规则错误量。 选择虚拟化电路设计中的一个用于制造电路设计，其中基于每个设计规则误差量进行选择。
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