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公开(公告)号：US20150178438A1
公开(公告)日：2015-06-25
申请号：US14137530
申请日：2013-12-20
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A first circuit design is entered in an electronic design automation (EDA) computer system. The first circuit design includes a first feature with a first node. A marker is associated with the first node and represents a voltage associated with the first node as an algebraic expression of a numerical value representing a property of the circuit design. The marker is used to determine if the component of the circuit design violates a design rule.
摘要翻译： 在电子设计自动化（EDA）计算机系统中输入第一电路设计。 第一电路设计包括具有第一节点的第一特征。 标记与第一节点相关联，并且表示与第一节点相关联的电压作为表示电路设计的属性的数值的代数表达式。 标记用于确定电路设计的组件是否违反了设计规则。
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2.发明申请公开(公告)号：US20080230873A1
公开(公告)日：2008-09-25
申请号：US11689657
申请日：2007-03-22
申请人： Ertugrul Demircan , Jack M. Higman
发明人： Ertugrul Demircan , Jack M. Higman
CPC分类号： H01L23/5223 , H01L23/5227 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor.
摘要翻译： 集成电路具有用于与集成电路进行电连接的多个端子。 在集成电路的外边缘附近形成至少一个器件。 该器件包括至少一个金属导体，用于形成用于在分模期间保护集成电路的边缘密封。 该装置通过将至少一个金属导体路由到一个或多个功能电路而耦合到集成电路内的一个或多个功能电路，所述至少一个装置向一个或多个功能电路提供电抗值用于非测试 操作使用。 该器件可以形成为一个或多个电容器或一个或多个电感器。 电容器和电感器可以使用各种结构。
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公开(公告)号：US07386821B2
公开(公告)日：2008-06-10
申请号：US11423240
申请日：2006-06-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for forming an integrated circuit (280) comprises accessing (282) a library of primitive cells and edge codes in the formation of an integrated circuit layout. At least one edge code of at least one previously placed primitive cell (284) of the integrated circuit layout is used. A primitive cell is selected (286) from the library that is compatible with the at least one previously placed primitive cell and the selected primitive cell is placed into the integrated circuit layout adjacent the at least one previously placed primitive cell. The integrated circuit is manufactured (290) using the integrated circuit layout.
摘要翻译： 一种用于形成集成电路（280）的方法包括在形成集成电路布局时访问（282）原始单元库和边缘码。 使用集成电路布局的至少一个先前放置的原始单元（284）的至少一个边缘码。 从库中选择原始单元（286），该库与至少一个先前放置的原始单元兼容，并且所选择的原始单元被放置在与至少一个先前放置的原始单元相邻的集成电路布局中。 使用集成电路布局制造集成电路（290）。
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公开(公告)号：US20080005717A1
公开(公告)日：2008-01-03
申请号：US11423240
申请日：2006-06-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for forming an integrated circuit (280) comprises accessing (282) a library of primitive cells and edge codes in the formation of an integrated circuit layout. At least one edge code of at least one previously placed primitive cell (284) of the integrated circuit layout is used. A primitive cell is selected (286) from the library that is compatible with the at least one previously placed primitive cell and the selected primitive cell is placed into the integrated circuit layout adjacent the at least one previously placed primitive cell. The integrated circuit is manufactured (290) using the integrated circuit layout.
摘要翻译： 一种用于形成集成电路（280）的方法包括在形成集成电路布局时访问（282）原始单元库和边缘码。 使用集成电路布局的至少一个先前放置的原始单元（284）的至少一个边缘码。 从库中选择原始单元（286），该库与至少一个先前放置的原始单元兼容，并且所选择的原始单元被放置在与至少一个先前放置的原始单元相邻的集成电路布局中。 使用集成电路布局制造集成电路（290）。
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5.发明授权Prioritized design for manufacturing virtualization with design rule checking filtering 有权用设计规则检查过滤制造虚拟化的优先设计公开(公告)号：US09026970B2
公开(公告)日：2015-05-05
申请号：US13788046
申请日：2013-03-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An approach is provided to generate a number of virtualized circuit designs by applying design-for-manufacturing (DFM) processes to a circuit design. The virtualized circuit designs are checked using design rule checks (DRCs), with the checking resulting in a design rule error quantity that corresponds to each of the virtualized circuit designs. One of the virtualized circuit designs is selected for use in manufacturing the circuit design with the selection based each of the design's design rule error quantities.
摘要翻译： 提供了一种通过将设计制造（DFM）处理应用于电路设计来生成多个虚拟化电路设计的方法。 使用设计规则检查（DRC）检查虚拟化电路设计，检查导致与每个虚拟化电路设计相对应的设计规则错误量。 选择虚拟化电路设计中的一个用于制造电路设计，其中基于每个设计规则误差量进行选择。
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6.发明授权公开(公告)号：US08713498B2
公开(公告)日：2014-04-29
申请号：US13216769
申请日：2011-08-24
申请人： Mehul D. Shroff , Ertugrul Demircan
发明人： Mehul D. Shroff , Ertugrul Demircan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A data processing system determines current information corresponding to a node included at a device design. Physical layout information corresponding to the node is received, the physical layout information including one or more layout geometries, the one or more layout geometries providing a circuit network. The circuit network may be partitioned into two or more network segments. A current conducted at a network segment is identified based on the current information. Information representative of dimensions and metal layer of a layout geometry included at the network segment is received. The computer determines that the current exceeds a predetermined maximum threshold, the predetermined maximum threshold determined based on the dimensions and metal layer.
摘要翻译： 数据处理系统确定与包括在设备设计中的节点相对应的当前信息。 接收对应于节点的物理布局信息，物理布局信息包括一个或多个布局几何形状，一个或多个布局几何形状提供电路网络。 电路网络可以被划分成两个或更多个网段。 基于当前信息，识别在网段进行的电流。 接收代表包括在网段中的布局几何尺寸和金属层的信息。 计算机确定电流超过预定的最大阈值，基于尺寸和金属层确定的预定最大阈值。
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公开(公告)号：US20130320490A1
公开(公告)日：2013-12-05
申请号：US13489139
申请日：2012-06-05
CPC分类号： H01L28/10 , H01F17/0006 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions.
摘要翻译： 半导体器件结构具有第一导电类型和顶表面的半导体衬底。 多个第一掺杂区域处于以棋盘方式布置的顶表面下方的第一深度。 第一掺杂区域是第二导电类型。 电介质层在顶表面之上。 电感元件在电介质层之上，其中电感元件在第一掺杂区域之上。
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8.发明申请公开(公告)号：US20110001214A1
公开(公告)日：2011-01-06
申请号：US12884807
申请日：2010-09-17
申请人： ERTUGRUL DEMIRCAN , JACK M. HIGMAN
发明人： ERTUGRUL DEMIRCAN , JACK M. HIGMAN
CPC分类号： H01L23/5223 , H01L23/5227 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor.
摘要翻译： 集成电路具有用于与集成电路进行电连接的多个端子。 在集成电路的外边缘附近形成至少一个器件。 该器件包括至少一个金属导体，用于形成用于在分模期间保护集成电路的边缘密封。 该装置通过将至少一个金属导体路由到一个或多个功能电路而耦合到集成电路内的一个或多个功能电路，所述至少一个装置向一个或多个功能电路提供电抗值用于非测试 操作使用。 该器件可以形成为一个或多个电容器或一个或多个电感器。 电容器和电感器可以使用各种结构。
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9.发明授权公开(公告)号：US09245086B2
公开(公告)日：2016-01-26
申请号：US14266499
申请日：2014-04-30
申请人： Ertugrul Demircan , Mehul D. Shroff
发明人： Ertugrul Demircan , Mehul D. Shroff
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F17/5068 , G06F17/5077 , G06F2217/82
摘要： A technique for electromigration stress mitigation in interconnects of an integrated circuit design includes generating a maximal spanning tree of a directed graph, which represents an interconnect network of an integrated circuit design. A first point on the spanning tree having a lowest stress and a second point on the spanning tree having a highest stress are located. A maximum first stress between the first and second points is determined. In response to determining the maximum first stress between the first and second points is greater than a critical stress, a stub is added to the spanning tree at a node between the first and second points. The maximum first stress between the first and second points is re-determined subsequent to adding the stub.
摘要翻译： 用于集成电路设计的互连中的电迁移应力减轻的技术包括生成有向图的最大生成树，其表示集成电路设计的互连网络。 位于具有最小应力的生成树上的第一点和具有最高应力的生成树上的第二点。 确定第一和第二点之间的最大第一应力。 响应于确定第一和第二点之间的最大第一应力大于临界压力，在第一和第二点之间的节点处将生物树添加到生成树。 第一点和第二点之间的最大第一应力在添加存根之后重新确定。
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公开(公告)号：US08766402B2
公开(公告)日：2014-07-01
申请号：US13489139
申请日：2012-06-05
CPC分类号： H01L28/10 , H01F17/0006 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions.
摘要翻译： 半导体器件结构具有第一导电类型和顶表面的半导体衬底。 多个第一掺杂区域处于以棋盘方式布置的顶表面下方的第一深度。 第一掺杂区域是第二导电类型。 电介质层在顶表面之上。 电感元件在电介质层之上，其中电感元件在第一掺杂区域之上。
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