Method of adding constrained cluster points to interconnection nets in
integrated circuit chips and packages
    1.
    发明授权
    Method of adding constrained cluster points to interconnection nets in integrated circuit chips and packages 失效
    将约束聚类点添加到集成电路芯片和封装中的互连网络的方法

    公开(公告)号:US6014508A

    公开(公告)日:2000-01-11

    申请号:US909112

    申请日:1997-08-11

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5077

    摘要: A method of wiring a plurality of integrated circuits within a chip or between chips in one or more packages by adding cluster points to a net that includes a plurality of nodes to be interconnected. The interconnected nodes are designed to meet system requirements, commonly expressed by a set of wiring rules, include among others, physical, electrical and noise constraints. The method includes matching interconnection net attributes to wiring rule logical definitions, wherein the wiring rules include rule nodes and rule connections. The rule nodes define constraints for the pins, vias and cluster point structures. The rule connections define wiring constraints between the node structures to establish the net topology. The process described is based on net ordering and checking. The net ordering, which defines the pin-to-pin connections based on the wiring rule, is performed prior to chip or package wiring. Net ordering imposes the wiring rule added cluster points, the desired interconnection topology and the wiring constraints to the net. Checking verifies the correctness of the net attributes when the design wiring is complete.

    摘要翻译: 一种通过向包括要互连的多个节点的网络添加集群点来在一个或多个包装中的芯片内或芯片之间布线多个集成电路的方法。 互连节点被设计为满足系统要求,通常由一组布线规则表示,包括物理,电气和噪声限制。 该方法包括将互连网络属性与布线规则逻辑定义相匹配,其中布线规则包括规则节点和规则连接。 规则节点定义了引脚,通孔和簇点结构的约束。 规则连接定义节点结构之间的布线约束以建立网络拓扑。 所描述的过程是基于网络排序和检查。 基于布线规则定义引脚到引脚连接的网络排序在芯片或封装布线之前执行。 网络排序强制布线规则添加了集群点,所需的互连拓扑和布线约束到网络。 当设计接线完成时,检查会验证网络属性的正确性。

    Method and apparatus for dynamically varying net rules
    2.
    发明授权
    Method and apparatus for dynamically varying net rules 失效
    动态变化网络规则的方法和装置

    公开(公告)号:US5757653A

    公开(公告)日:1998-05-26

    申请号:US648800

    申请日:1996-05-16

    IPC分类号: H01L23/12 G06F17/50

    CPC分类号: G06F17/509 G06F17/5077

    摘要: Permutations of orders of elements such as electrical connection pins, vias and t-junctions at known locations are efficiently tested against at least type and distance criteria by forming a plurality of lists of the elements and screening the elements of each list against respective ones of said type criteria to reduce the length of the lists of elements. Pointers to ones of the distance criteria and remaining members of a list corresponding to respective ones of the distance criteria iteratively form pairs of elements which are checked for separation. When the check fails or a solution is found, the pointer to list members is advanced. The pointer to respective distance criteria is advanced when a check is successful. When a list is exhausted and a check is unsuccessful, the pointer to respective distance criteria is regressed. Advancement and regression of pointers reduces iterations of combinations of pairs of elements which do not lead to a solution in order to accelerate the process. Each new solution is evaluated against a single stored prior solution for optimization of solutions while greatly reducing storage requirements.

    摘要翻译: 通过形成多个元件列表并根据相应的所述元件筛选每个列表的元素,来有效地对至少类型和距离标准来测试已知位置处的诸如电连接引脚,通孔和T形接头之类的元件的顺序的排列 键入标准以减少元素列表的长度。 指向距离标准中的一个的指针和与各个距离标准相对应的列表的剩余成员迭代地形成检查分离的元素对。 当检查失败或找到解决方案时,指向列表成员的指针是高级的。 当检查成功时,指向相应距离标准的指针会提前。 当列表用尽并且检查不成功时,指向相应距离标准的指针被退化。 指针的推进和回归减少了不会导致解决方案的元素对的组合的迭代,以加速过程。 每个新解决方案都针对单一存储的先前解决方案进行评估,以优化解决方案,同时大大减少存储要求。