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    Techniques for grouping circuit elements into logic blocks
    1.
    发明授权
    Techniques for grouping circuit elements into logic blocks 失效
    将电路元件分组成逻辑块的技术

    公开(公告)号：US07707532B1

    公开(公告)日：2010-04-27

    申请号：US11844216

    申请日：2007-08-23

    申请人： Ketan Padalia ,  Kimberly Bozman ,  Vaughn Betz

    发明人： Ketan Padalia ,  Kimberly Bozman ,  Vaughn Betz

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  Y02T10/82

    摘要： Techniques are provided for grouping circuits in a user design for a programmable integrated circuit into logic blocks. A packing tool separates each circuit element into individual abstract blocks and groups the abstract block into logic blocks. A determination is made whether placement information indicates that a design goal would be improved by rearranging at least a portion of the user design. The user design can be rearranged by moving one or more of the abstract blocks into different logic blocks than the ones they were previously grouped with. Circuit elements in the same logic block can be separated and placed into different logic blocks to improve routability of the user design and signal timing.

    摘要翻译： 提供了用于将可编程集成电路的用户设计中的电路分组成逻辑块的技术。 包装工具将每个电路元件分成单独的抽象块，并将抽象块分组成逻辑块。 确定放置信息是否指示通过重新排列用户设计的至少一部分来提高设计目标。 可以通过将抽象块中的一个或多个移动到与之前分组的逻辑块不同的逻辑块中来重新排列用户设计。 相同逻辑块中的电路元件可以分离并放置到不同的逻辑块中，以改善用户设计和信号时序的可布线性。

    Techniques for grouping circuit elements into logic blocks
    2.
    发明授权
    Techniques for grouping circuit elements into logic blocks 有权
    将电路元件分组成逻辑块的技术

    公开(公告)号：US07275228B1

    公开(公告)日：2007-09-25

    申请号：US10716309

    申请日：2003-11-17

    申请人： Ketan Padalia ,  Kimberly Bozman ,  Vaughn Betz

    发明人： Ketan Padalia ,  Kimberly Bozman ,  Vaughn Betz

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  Y02T10/82

    摘要： Techniques are provided for grouping circuits in a user design for a programmable integrated circuit into logic blocks. A packing tool separates each circuit element into individual abstract blocks and groups the abstract block into logic blocks. A determination is made whether placement information indicates that a design goal would be improved by rearranging at least a portion of the user design. The user design can be rearranged by moving one or more of the abstract blocks into different logic blocks than the ones they were previously grouped with. Circuit elements in the same logic block can be separated and placed into different logic blocks to improve routability of the user design and signal timing.

    摘要翻译： 提供了用于将可编程集成电路的用户设计中的电路分组成逻辑块的技术。 包装工具将每个电路元件分成单独的抽象块，并将抽象块分组成逻辑块。 确定放置信息是否指示通过重新排列用户设计的至少一部分来提高设计目标。 可以通过将抽象块中的一个或多个移动到与之前分组的逻辑块不同的逻辑块中来重新排列用户设计。 相同逻辑块中的电路元件可以分离并放置到不同的逻辑块中，以改善用户设计和信号时序的可布线性。

    Automatic adjustment of optimization effort in configuring programmable devices
    4.
    发明申请
    Automatic adjustment of optimization effort in configuring programmable devices 有权
    自动调整配置可编程设备的优化工作

    公开(公告)号：US20060225021A1

    公开(公告)日：2006-10-05

    申请号：US11097592

    申请日：2005-04-01

    申请人： Ketan Padalia ,  Jason Peters ,  Vaughn Betz

    发明人： Ketan Padalia ,  Jason Peters ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： User designs are assigned to a category for each design goal associated with the user design. Each category represents the difficulty of satisfying a design goal. Optimization phases are tailored to different combinations of categories and are selected according to the categories assigned to the user design. A ranking of the relative difficulty of the design goals is determined from the categories associated with the user design. Parameters of an optimization phase can be modified in accordance with this ranking to focus optimization efforts on specific design goals. The parameters may be weights of a cost function used by the optimization phase to evaluate alternative configurations of the user design. The user design can be re-classified into an additional category if the results of the optimization phase do not satisfy design goals, and additional optimization phases are selected based on this re-classification to further optimize the user design.

    摘要翻译： 用户设计被分配到与用户设计相关联的每个设计目标的类别。 每个类别代表满足设计目标的难度。 优化阶段根据类别的不同组合进行调整，并根据分配给用户设计的类别进行选择。 根据与用户设计相关的类别确定设计目标相对难度的排名。 优化阶段的参数可以根据这个排名进行修改，将优化工作集中在具体的设计目标上。 参数可以是优化阶段用于评估用户设计的替代配置的成本函数的权重。 如果优化阶段的结果不满足设计目标，则可以将用户设计重新分类为另外的类别，并且基于该重新分类来选择额外的优化阶段以进一步优化用户设计。

    Automatic adjustment of optimization effort in configuring programmable devices
    5.
    发明授权
    Automatic adjustment of optimization effort in configuring programmable devices 有权
    自动调整配置可编程设备的优化工作

    公开(公告)号：US07415682B2

    公开(公告)日：2008-08-19

    申请号：US11097592

    申请日：2005-04-01

    申请人： Ketan Padalia ,  Jason Peters ,  Vaughn Betz

    发明人： Ketan Padalia ,  Jason Peters ,  Vaughn Betz

    IPC分类号： G06F17/50 ,  H03K17/693

    CPC分类号： G06F17/5054

    摘要： User designs are assigned to a category for each design goal associated with the user design. Each category represents the difficulty of satisfying a design goal. Optimization phases are tailored to different combinations of categories and are selected according to the categories assigned to the user design. A ranking of the relative difficulty of the design goals is determined from the categories associated with the user design. Parameters of an optimization phase can be modified in accordance with this ranking to focus optimization efforts on specific design goals. The parameters may be weights of a cost function used by the optimization phase to evaluate alternative configurations of the user design. The user design can be re-classified into an additional category if the results of the optimization phase do not satisfy design goals, and additional optimization phases are selected based on this re-classification to further optimize the user design.

    摘要翻译： 用户设计被分配到与用户设计相关联的每个设计目标的类别。 每个类别代表满足设计目标的难度。 优化阶段根据类别的不同组合进行调整，并根据分配给用户设计的类别进行选择。 根据与用户设计相关的类别确定设计目标相对难度的排名。 优化阶段的参数可以根据这个排名进行修改，将优化工作集中在具体的设计目标上。 参数可以是优化阶段用于评估用户设计的替代配置的成本函数的权重。 如果优化阶段的结果不满足设计目标，则可以将用户设计重新分类为另外的类别，并且基于该重新分类来选择额外的优化阶段以进一步优化用户设计。

    Apparatus and Methods for Parallelizing Integrated Circuit Computer-Aided Design Software
    7.
    发明申请
    Apparatus and Methods for Parallelizing Integrated Circuit Computer-Aided Design Software 审中-公开
    并联集成电路计算机辅助设计软件的装置与方法

    公开(公告)号：US20100070979A1

    公开(公告)日：2010-03-18

    申请号：US12545224

    申请日：2009-08-21

    申请人： Adrian Ludwin ,  Vaughn Betz ,  Ketan Padalia

    发明人： Adrian Ludwin ,  Vaughn Betz ,  Ketan Padalia

    IPC分类号： G06F9/46

    CPC分类号： G06F9/4881 ,  G06F2209/483 ,  G06F2209/484

    摘要： A system for parallelizing software in computer-aided design (CAD) software for logic design includes a computer. The computer is configured to identify dependencies among a set of tasks. The computer is also configured to perform the set of tasks in parallel such that a solution of a problem is identical to a solution produced by performing the set of tasks serially.

    摘要翻译： 用于并行化用于逻辑设计的计算机辅助设计（CAD）软件中的软件的系统包括计算机。 计算机被配置为识别一组任务之间的依赖关系。 计算机还被配置为并行地执行一组任务，使得问题的解决方案与通过一致地执行该任务所产生的解决方案相同。

    Methods for designing integrated circuits
    8.
    发明授权
    Methods for designing integrated circuits 有权
    集成电路设计方法

    公开(公告)号：US07441208B1

    公开(公告)日：2008-10-21

    申请号：US11225919

    申请日：2005-09-13

    申请人： Ketan Padalia ,  Vaughn Betz ,  Vadim Gouterman

    发明人： Ketan Padalia ,  Vaughn Betz ,  Vadim Gouterman

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： The process of designing an integrated circuit (“IC”) to implement a generalized circuit design includes a signoff between a front-end part of the process and a back-end part of the process. This signoff preferably takes place after at least some global routing has been done for the IC implementation, but before all final detailed routing is done for that implementation.

    摘要翻译： 设计集成电路（“IC”）以实现广义电路设计的过程包括过程的前端部分与过程的后端部分之间的签名。 这种签名优选在对IC实现进行至少一些全局路由之后，但在为该实现完成所有最终详细路由之前进行。

    Apparatus and methods for parallelizing integrated circuit computer-aided design software
    9.
    发明申请
    Apparatus and methods for parallelizing integrated circuit computer-aided design software 审中-公开
    用于并行集成电路计算机辅助设计软件的装置和方法

    公开(公告)号：US20070192766A1

    公开(公告)日：2007-08-16

    申请号：US11392215

    申请日：2006-03-29

    申请人： Ketan Padalia ,  Adrian Ludwin ,  Vaughn Betz ,  Ryan Fung

    发明人： Ketan Padalia ,  Adrian Ludwin ,  Vaughn Betz ,  Ryan Fung

    IPC分类号： G06F9/46

    CPC分类号： G06F8/45 ,  G06F17/5054

    摘要： A system for providing parallelization in computer aided design (CAD) software includes a computer. The computer is configured to identify a set of tasks having local independence, and assign each task in the set of tasks to be performed in parallel. The computer is further configured to perform each task in the set of tasks.

    摘要翻译： 用于在计算机辅助设计（CAD）软件中提供并行化的系统包括计算机。 计算机被配置为识别具有本地独立性的一组任务，并且将要并行执行的任务集中的每个任务分配。 计算机还被配置为在该组任务中执行每个任务。

    Method and apparatus for implementing cross-talk based booster wires in a system on a field programmable gate array
    10.
    发明授权
    Method and apparatus for implementing cross-talk based booster wires in a system on a field programmable gate array 有权
    用于在现场可编程门阵列上的系统中实现基于串扰的升压线的方法和装置

    公开(公告)号：US08468487B1

    公开(公告)日：2013-06-18

    申请号：US12386739

    申请日：2009-04-22

    申请人： Zahir Parpia ,  Chris Wysocki ,  Vaughn Betz

    发明人： Zahir Parpia ,  Chris Wysocki ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F17/5077

    摘要： A method for designing a system on a field programmable gate array (FPGA) includes routing one or more booster wires alongside an interconnect to reduce a delay of a signal being transmitted on the interconnect. According to one aspect of the present invention, the routing of the one or more booster wires is performed in response to determining that a timing requirement of the system has not been met.

    摘要翻译： 用于在现场可编程门阵列（FPGA）上设计系统的方法包括在互连旁边布置一个或多个升压线，以减少在互连上传输的信号的延迟。 根据本发明的一个方面，响应于确定尚未满足系统的定时要求，执行一个或多个升压线的路由。