公开(公告)号：US08468487B1

公开(公告)日：2013-06-18

申请号：US12386739

申请日：2009-04-22

申请人： Zahir Parpia ,  Chris Wysocki ,  Vaughn Betz

发明人： Zahir Parpia ,  Chris Wysocki ,  Vaughn Betz

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5077

摘要： A method for designing a system on a field programmable gate array (FPGA) includes routing one or more booster wires alongside an interconnect to reduce a delay of a signal being transmitted on the interconnect. According to one aspect of the present invention, the routing of the one or more booster wires is performed in response to determining that a timing requirement of the system has not been met.

摘要翻译： 用于在现场可编程门阵列（FPGA）上设计系统的方法包括在互连旁边布置一个或多个升压线，以减少在互连上传输的信号的延迟。 根据本发明的一个方面，响应于确定尚未满足系统的定时要求，执行一个或多个升压线的路由。

公开(公告)号：US08704549B1

公开(公告)日：2014-04-22

申请号：US13464869

申请日：2012-05-04

申请人： Zahir Parpia ,  Chris Wysocki

发明人： Zahir Parpia ,  Chris Wysocki

IPC分类号： H03K19/173

CPC分类号： G05F1/46 ,  H03K19/0016 ,  H03K19/0175 ,  H03K19/17736

摘要： Programmable integrated circuits with configurable logic circuitry and routing resources are provided. Portions of the routing resources on a programmable integrated circuit may be used in implementing a desired user-specified custom logic function, whereas other portions of the routing resources on the programmable integrated circuit may be unused. The unused routing resources may include adjacent pairs of routing paths. These paths may be coupled to control circuitry configured to drive the routing paths to desired voltage levels to provide an optimal amount of decoupling capacitance. In one suitable arrangement, two adjacent routing paths may both be driven to a positive power supply voltage level. In another suitable arrangement, the two adjacent routing paths may be driven to the positive power supply voltage level and a ground power supply voltage level, respectively.

摘要翻译： 提供了具有可配置逻辑电路和路由资源的可编程集成电路。 可编程集成电路上的路由资源的部分可以用于实现期望的用户指定的定制逻辑功能，而可编程集成电路上的路由资源的其他部分可能未被使用。 未使用的路由资源可以包括相邻的路由路由对。 这些路径可以耦合到被配置为将路由路径驱动到期望的电压电平以提供最佳量的去耦电容的控制电路。 在一个合适的布置中，两个相邻的路由路径都可以被驱动到正电源电压电平。 在另一种合适的布置中，两个相邻路由路径可分别被驱动到正电源电压电平和地电源电压电平。

公开(公告)号：US06937064B1

公开(公告)日：2005-08-30

申请号：US10280723

申请日：2002-10-24

申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

公开(公告)号：US07432734B2

公开(公告)日：2008-10-07

申请号：US11743625

申请日：2007-05-02

申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

公开(公告)号：US20070252617A1

公开(公告)日：2007-11-01

申请号：US11743625

申请日：2007-05-02

申请人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  ALexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

发明人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  ALexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

IPC分类号： H03K19/177

CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

公开(公告)号：US06970014B1

公开(公告)日：2005-11-29

申请号：US10623709

申请日：2003-07-21

申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

IPC分类号： H03K19/177

CPC分类号： H03K19/17736

摘要： An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width. In another configuration, the number of pins on one of the first side, the second side, or the third side differs from the number of pins on another one of those sides.

摘要翻译： 本发明的实施例涉及在可编程逻辑器件（“PLD”）内互连诸如逻辑阵列块（“LAB”）的功能块的3边路由架构。 在三面路由架构中，功能块第一侧的输入和输出连接到第一通道，功能块第二侧上的输入和输出连接到第二通道，其中第二侧与第一通道相反 侧。 功能块第三侧的输入和输出连接到第三个通道。 与功能块的第四侧相关联的与第三侧相反的第四侧的第四通道仅耦合到第一通道和第二通道。 在一种配置中，第一侧，第二侧和第三侧中的每一个上的输入和输出具有相等数量的输入和输出。 在该配置中，第一通道，第二通道和第三通道中的每一个具有相同的宽度。 在另一种构造中，第一侧，第二侧或第三侧中的一个上的引脚数目与另一侧上的引脚数不同。

公开(公告)号：US07671626B1

公开(公告)日：2010-03-02

申请号：US12202053

申请日：2008-08-29

申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/177

摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

公开(公告)号：US20050127944A1

公开(公告)日：2005-06-16

申请号：US11050111

申请日：2005-02-02

申请人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

发明人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

公开(公告)号：US06630842B1

公开(公告)日：2003-10-07

申请号：US10140287

申请日：2002-05-06

申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

IPC分类号： H03K19177

CPC分类号： H03K19/17736

摘要： An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width. In another configuration, the number of pins on one of the first side, the second side, or the third side differs from the number of pins on another one of those sides. In this configuration, the width of one of the first channel, the second channel, or the third channel differs from the width of another one of those channels. Input multiplexers route signals from the wires of the channels to the inputs of the function block. Output multiplexers and drivers drive the outputs of the function block through the wires of the channels. By placing the input multiplexers and the output multiplexers in certain relative arrangements, the logical distance that an output signal from the function block can travel on a wire is increased and that signal can be looped back to itself. In addition, each of the inputs and the outputs of the function block can be connected to both horizontal and vertical channels, and an output of the function block can be directly connected to an input of an adjacent function block.

公开(公告)号：US08286109B1

公开(公告)日：2012-10-09

申请号：US13118471

申请日：2011-05-30

申请人： Derek So ,  Chris Wysocki

发明人： Derek So ,  Chris Wysocki

IPC分类号： G06F9/45 ,  G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5054

摘要： A method for designing a system on a target device includes identifying components and routing connections impacted by incremental design changes made to a system design. New information is computed to annotate delays for the components and routing connections identified. Delays previously computed for components and routing connections are utilized to annotate delays for components and routing connections that have not been impacted by the changes made to the system design.

摘要翻译： 用于在目标设备上设计系统的方法包括识别由对系统设计进行的增量设计改变而影响的组件和路由连接。 计算新信息以注释组件和所识别的路由连接的延迟。 先前为组件和路由连接计算的延迟用于注释未受系统设计更改影响的组件和路由连接的延迟。