Electronic circuit breaker using digital circuitry having instantaneous
trip capability
    2.
    发明授权
    Electronic circuit breaker using digital circuitry having instantaneous trip capability 失效
    具有瞬时跳闸功能的数字电路的电子断路器

    公开(公告)号:US4943888A

    公开(公告)日:1990-07-24

    申请号:US377373

    申请日:1989-07-10

    IPC分类号: G01R31/02 H02H3/093

    CPC分类号: H02H3/0935

    摘要: Instantaneous trip capability is provided to an electronic circuit breaker, which is of the type that generates trip signals by accumulating squares of power line current samples and thresholds the accumulation results. Samples of power line current are taken directly from the current transformer and analog-to-digital converter cascade generating them. The analog-to-digital converter is of an oversampling type, using a delta-sigma modulator. The samples are threshold detected against a prescribed threshold value without previous squaring, integration and detection. The threshold detector result is checked for two consecutive overcurrent indications before an instantaneous trip signal is generated.

    摘要翻译: 电子断路器提供瞬时跳闸能力,该电子断路器是通过累积电力线电流样本的平方并产生累积结果来产生跳闸信号的类型。 电力线电流的样本直接从电流互感器和模数转换器级联产生。 模数转换器是采用Δ-Σ调制器的过采样类型。 样本相对于规定的阈值进行阈值检测,无需先前的平方,积分和检测。 在产生瞬时跳闸信号之前,对两个连续的过电流指示进行阈值检测结果的检查。

    Subsampling time-domain digital filter using sparsely clocked output
latch
    3.
    发明授权
    Subsampling time-domain digital filter using sparsely clocked output latch 失效
    使用稀疏时钟输出锁存器的子采样时域数字滤波器

    公开(公告)号:US4982353A

    公开(公告)日:1991-01-01

    申请号:US414869

    申请日:1989-09-28

    IPC分类号: G06F5/06 G06F7/62

    CPC分类号: G06F7/62 G06F5/06

    摘要: The plural-phase clocking signal used in a subsampling time-domain digital filter is partially blanked to generate a sparse clocking signal for a clocked data latch that decimates the output signal from the digital filter, to supply it at a subsampling rate as compared to the sampling rate of input signal to the filter. The blanking signal is generated from a counter that counts occurrences of pulses in the plural-phase clocking signal, which counter comprises a ripple-carry adder and another clocked data latch arranged to accumulate successive unit values. This procedure guarantees correct timing of clocking signal for the output latch vis-a-vis the plural-phase clocking signal used in the preceding time-domain digital filter despite the time taken for carry ripplethrough in the counter adder. Digital hardware is conserved by blanking only one phase of the plural-phase clocking signals.

    摘要翻译: 在子采样时域数字滤波器中使用的多相时钟信号被部分消隐,以产生用于对来自数字滤波器的输出信号进行抽取的时钟数据锁存器的稀疏时钟信号,以将其与子采样时间信号 输入信号到滤波器的采样率。 消隐信号由计数器产生,该计数器对多相时钟信号中的脉冲发生进行计数,该计数器包括纹波进位加法器和另一个计时数据锁存器,被布置为累积连续的单位值。 尽管在计数器加法器中进行进位纹波的时间,该过程保证输出锁存器对于前一时域数字滤波器中使用的多相时钟信号的时钟信号的正确定时。 数字硬件通过仅消除多相时钟信号的一相来节省。