公开(公告)号：US20080082883A1

公开(公告)日：2008-04-03

申请号：US11531035

申请日：2006-09-12

申请人： Kevin W Gorman ,  Emory D. Keller ,  Michael R. Ouellette ,  Donald L. Wheater

发明人： Kevin W Gorman ,  Emory D. Keller ,  Michael R. Ouellette ,  Donald L. Wheater

IPC分类号： G01R31/28

CPC分类号： G11C29/44 ,  G11C2029/3202

摘要： A system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.

摘要翻译： 公开了一种通过内置自检（BIST）执行高速存储器诊断的系统和方法。 特别地，测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。 测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。 通过BIST执行高速存储器诊断的方法包括但不限于预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑的等待时间的值，设置BIST周期计数器 将可变延迟预置为零，重新执行测试算法并执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。