公开(公告)号：US20220300576A1

公开(公告)日：2022-09-22

申请号：US17470996

申请日：2021-09-09

Applicant: Kioxia Corporation

Inventor： Hajime MATSUI

IPC: G06F17/16

Abstract: A controller of a computing apparatus calculates aP by multiplying an integer a being 2 or more and less than 2w and a coordinate value P; reads out, by w bits, a multiplication value k being a bit string and generates a string of signed odd numbers d of w+1 bits; calculates dP by multiplying a head of the d and the P and inputs the dP to a variable; executes looping between processing for inputting, to the variable, a value obtained by doubling the variable w times and processing for calculating dP by multiplying the P and a second or after of the d and inputting, to the variable, an addition result of the dP and the variable; and calculates a value by multiplying the P and a value based on lower 2 bits of the k and outputs kP by adding the calculated value and the variable.

公开(公告)号：US20220083624A1

公开(公告)日：2022-03-17

申请号：US17197256

申请日：2021-03-10

Applicant: Kioxia Corporation

Inventor： Hajime MATSUI

IPC: G06F17/16 ,  G06F7/50 ,  G06F12/14

Abstract: According to one embodiment, in an inverse element arithmetic apparatus, a word unit processing unit, as approximate calculation loop for extended binary GCD process, iterates a first loop in a case where a value of |r−s| is a subtraction threshold or more, and is capable of iterating a second loop instead of the first loop in a case where the value of |r−s| is smaller than the subtraction threshold. In the first loop, values of r, s, a, b, m, and n is updated and an update matrix M is generated or updated. In the second loop, the values of m and n are updated without updating the values of r, s, a, b and the update matrix M. The control unit terminates the loop of the inverse element arithmetic process in a case where a loop number of times of the inverse element arithmetic process reaches a number-of-times threshold.

公开(公告)号：US20240250831A1

公开(公告)日：2024-07-25

申请号：US18536003

申请日：2023-12-11

Applicant: Kioxia Corporation

Inventor： Hajime MATSUI

IPC: H04L9/32 ,  G06F8/65 ,  G06F21/57

CPC classification number: H04L9/3247 ,  G06F8/65 ,  G06F21/575 ,  G06F2221/034

Abstract: According to one embodiment, a controller includes a CPU and an accelerator which performs signature verification using a first signature of a first scheme. When updating first firmware to second firmware to which a second signature of a second scheme is assigned, the controller performs the signature verification of the second firmware based on the second signature assigned to the second firmware by the CPU, generates the first signature for the second firmware, and replaces the second signature assigned to the second firmware with the generated first digital signature. When booting the second firmware, the controller performs the signature verification of the second firmware based on the first signature assigned to the second firmware by the accelerator.

公开(公告)号：US20230093203A1

公开(公告)日：2023-03-23

申请号：US17643615

申请日：2021-12-10

Applicant: Kioxia Corporation

Inventor： Hajime MATSUI

IPC: G06F7/72

Abstract: According to an embodiment, an arithmetic device outputting an arithmetic result on a finite field with characteristic P includes a hardware processor. The hardware processor performs readout processing of a plurality of input values. The hardware processor performs, for each word, arithmetic operations with respect to the plurality of input values by using a value being based on the characteristic P and a comparison value between each input value of the plurality of input values and the characteristic P. The hardware processor outputs a first output value resulting from computing a value being based on each input value of the plurality of input values, the comparison value, and the characteristic P. The hardware processor outputs a second output value resulting from comparing the first output value and the characteristic P.

公开(公告)号：US20230071555A1

公开(公告)日：2023-03-09

申请号：US17653567

申请日：2022-03-04

Applicant: Kioxia Corporation

Inventor： Takaya OGAWA ,  Hajime MATSUI

IPC: G06F12/14 ,  G06F12/02 ,  G06F21/60

Abstract: According to one embodiment, a key search circuit includes a hit determination circuit that determines whether a key search request hits a content stored in a search result buffer, and an update determination circuit that determines whether to update the content stored in the search result buffer. When the hit determination circuit determines that the key search request hits the search result buffer, the key search circuit outputs the search result stored in the search result buffer to an encryption/decryption circuit. When the update determination circuit determines to update the search result buffer, the key search circuit updates the content stored in the search result buffer with the key search request and a search result obtained from a range table.