公开(公告)号：US20250013759A1

公开(公告)日：2025-01-09

申请号：US18743458

申请日：2024-06-14

Applicant: Kioxia Corporation

Inventor： Keiri NAKANISHI ,  Takaya OGAWA ,  Takashi TAKEMOTO ,  Kohei OIKAWA

IPC: G06F21/60

Abstract: A controller of a memory system includes circuitry that generates a first compression unit that is calculated based on first namespace setting information indicating setting of a write-destination namespace, and corresponds to the write-destination namespace. The first compression unit has a size satisfying a constraint that an encryption key for encrypting data to be written into the write-destination namespace is not switched in the first compression unit.

公开(公告)号：US20230071555A1

公开(公告)日：2023-03-09

申请号：US17653567

申请日：2022-03-04

Applicant: Kioxia Corporation

Inventor： Takaya OGAWA ,  Hajime MATSUI

IPC: G06F12/14 ,  G06F12/02 ,  G06F21/60

Abstract: According to one embodiment, a key search circuit includes a hit determination circuit that determines whether a key search request hits a content stored in a search result buffer, and an update determination circuit that determines whether to update the content stored in the search result buffer. When the hit determination circuit determines that the key search request hits the search result buffer, the key search circuit outputs the search result stored in the search result buffer to an encryption/decryption circuit. When the update determination circuit determines to update the search result buffer, the key search circuit updates the content stored in the search result buffer with the key search request and a search result obtained from a range table.

公开(公告)号：US20210082511A1

公开(公告)日：2021-03-18

申请号：US16805369

申请日：2020-02-28

Applicant: KIOXIA CORPORATION

Inventor： Takaya OGAWA

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor storage device includes: a memory cell array including a memory cell transistor that is an electrically rewritable non-volatile semiconductor storage element. The memory cell transistor includes a gate electrode and a channel region adjacent the gate electrode. The semiconductor storage device includes a circuit configured to write the memory cell transistor by applying a breakdown voltage to cause dielectric breakdown between the gate electrode and the channel region.