公开(公告)号：US20230072833A1

公开(公告)日：2023-03-09

申请号：US17578803

申请日：2022-01-19

Applicant: Kioxia Corporation

Inventor： Hiroki MITO ,  Daigo ICHINOSE

IPC: G11C5/06 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11551 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11578 ,  H01L23/528

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a lower interconnect, a source line, word lines, a pillar, a pattern portion, a contact. The source line is provided in a first layer above the lower interconnect. The pattern portion is provided to be separated and insulated from the source line in the first layer. A contact is extending in a first direction, penetrating the pattern portion, and provided on the lower interconnect. A width of the contact in a second direction parallel to a surface of the substrate differs between a portion above a boundary plane that is included in the first layer and is parallel to the surface of the substrate, and a portion below the boundary plane.