公开(公告)号：US20230057303A1

公开(公告)日：2023-02-23

申请号：US17679667

申请日：2022-02-24

Applicant: Kioxia Corporation

Inventor： Hiroyuki ISHII ,  Yuji NAGAI ,  Makoto MIAKASHI ,  Tomoko KAJIYAMA ,  Hayato KONNO

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

Abstract: A memory device includes a plurality of memory cell transistors, a first word line, a controller, and a storage circuit. Each of the plurality of memory cell transistors stores a plurality of pieces of bit data. The first word line is connected to a plurality of first memory cell transistors in the plurality of memory cell transistors. The controller performs a loop process including repetition of a program loop including a program operation and a first verification operation. The storage circuit stores status information. The controller performs the loop process, then performs a second verification operation, and stores first status data corresponding to a result of the loop process and second status data corresponding to a result of the second verification operation in the storage circuit, in a write operation using the plurality of first memory cell transistors as targets.