公开(公告)号：US11694995B2

公开(公告)日：2023-07-04

申请号：US17188308

申请日：2021-03-01

Applicant: Kioxia Corporation

Inventor： Michihito Kono ,  Takashi Izumida ,  Tadayoshi Uechi ,  Takeshi Shimane

IPC: H10B43/40 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40 ,  H01L2224/08145 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device, includes: a first region including a memory cell array; and a second region including a peripheral circuit. The second region includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes: a semiconductor region between the first and second surfaces; an n-type semiconductor region provided on the first surface and higher in donor concentration than the semiconductor region; a damaged region provided on the second surface; and a p-type semiconductor region provided between the damaged region and the n-type semiconductor region, closer to the second surface than the n-type semiconductor region in a direction from the first surface toward the second surfaces of the semiconductor substrate, and higher in acceptor concentration than the semiconductor region.