公开(公告)号：US11183256B2

公开(公告)日：2021-11-23

申请号：US16914733

申请日：2020-06-29

Applicant: Kioxia Corporation

Inventor： Koichi Shinohara ,  Katsuki Matsudera ,  Ian Christopher Gamara ,  Yoshikazu Harada ,  Noritaka Kai ,  Yusuke Tanefusa

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/14 ,  G11C16/08 ,  G06F9/30 ,  G11C16/24

Abstract: According to a certain embodiment, the semiconductor memory device includes a memory cell array, a control circuit, and a data register storing an erase verify fail flag. An erase target block is divided into word line groups. The control circuit includes: a counter configured to count the number of the erase verify fail flags to be output as a count value for each group; a plurality of counter registers configured to store the count value for each group; an arithmetic circuit configured to take a difference of the plurality of count values respectively stored in the plurality of counter registers and to output a result of the difference as a number of second fail flags; and a comparator configured to compare the number of criteria of the erase verify fail flag and the number of the second fail flags to be output as a memory state detected result.