公开(公告)号：US20220302155A1

公开(公告)日：2022-09-22

申请号：US17446865

申请日：2021-09-03

Applicant: Kioxia Corporation

Inventor： Ayumi WATARAI ,  Osamu MATSUURA ,  Taro KUSUMOTO ,  Sota MATSUMOTO

IPC: H01L27/11578 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11551

Abstract: A semiconductor memory device according to an embodiment includes: a first stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one, the first stacked body including a stair portion processed into a stair shape extending in a first direction such that the plurality of conductive layers forms terrace surfaces; an insulating film covering an upper portion of the first stacked body including the stair portion; and a first plate-like portion that extends in the first direction in the stair portion and penetrates the first stacked body, the first plate-like portion including a plurality of bridge portions that are arranged locally on an upper end portion side and intermittently in the first direction to couple parts of the insulating film arranged on both sides of the first plate-like portion to each other.

公开(公告)号：US20220399275A1

公开(公告)日：2022-12-15

申请号：US17643917

申请日：2021-12-13

Applicant: Kioxia Corporation

Inventor： So HIKOSAKA ,  Akiko NOMACHI ,  Osamu MATSUURA

IPC: H01L23/535 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor memory device includes: a stacked structure including first layers including conductive layers disposed in a first and a third regions and insulating layers disposed in a second region, first to third insulating members extending in a stacking direction, semiconductor layers disposed in the first and the third regions, and a contact electrode disposed in the second region. The first and the third insulating members extend across the first to third regions and the second insulating member extends across the first and the third regions. The second insulating member contacts the insulating layers. The first layers extend in a direction in the second region from a side of the first insulating member to a side of the third insulating member. The conductive layers in the first and the third regions are mutually connected via conductive layers in the second region.

公开(公告)号：US20220085052A1

公开(公告)日：2022-03-17

申请号：US17202690

申请日：2021-03-16

Applicant: Kioxia Corporation

Inventor： Ayumi WATARAI ,  Taichi IWASAKI ,  Osamu MATSUURA ,  Yu HIROTSU ,  Sota MATSUMOTO

IPC: H01L27/11578 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  G11C8/14

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, an outer peripheral conductive layer, a lower layer conductive layer, and a first contact. The substrate includes a core region and a first region. The outer peripheral conductive layer is provided to surround the core region in the first region. The outer peripheral conductive layer is included in a first layer. The lower layer conductive layer is provided in the first region. The first contact is provided on the lower layer conductive layer to surround the core region in the first region. An upper end of the first contact is included in the first layer. The first contact is electrically connected to the outer peripheral conductive layer.

公开(公告)号：US20220262744A1

公开(公告)日：2022-08-18

申请号：US17411238

申请日：2021-08-25

Applicant: Kioxia Corporation

Inventor： Mitsunori MASAKI ,  Hisashi KATO ,  Kazuhiro NOJIMA ,  Shoichi MIYAZAKI ,  Akira YOTSUMOTO ,  Kanako SHIGA ,  Yu HIROTSU ,  Osamu MATSUURA

IPC: H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: Semiconductor memory device includes: a first and second member each extending in a first direction in a boundary part between a first and second block region and arranged in the first direction; a support pillar arranged between the first and second member at the boundary part; conductive layers separated from one another and arranged in a third direction and split by the first and second member, and the support pillar into a first and second portion; and a memory pillar penetrating through the conductive layers. The support pillar includes a lower and upper pillar. A side face of the lower pillar and an extension of a side face of the upper pillar are displaced from each other in a plane based on a second and the third direction.