公开(公告)号：US20210074711A1

公开(公告)日：2021-03-11

申请号：US16797331

申请日：2020-02-21

Applicant: Kioxia Corporation

Inventor： Yusaku SUZUKI ,  Kazuhiro NOJIMA ,  Atsuko AIBA

IPC: H01L27/1157 ,  G11C16/04 ,  H01L27/11565

Abstract: A semiconductor memory device according to an embodiment includes a base, a first conductor, a second conductor, a first pillar, a first insulating member, and a first contact. The first conductor is provided in a first layer above the base. The second conductor is provided above the first conductor. The first pillar includes a first portion and a second portion formed by different bodies. The first portion of the first pillar is provided to penetrate the first conductor. The second portion of the first pillar is provided to penetrate the second conductor. The first insulating member is provided at least in the first layer. The first contact is contacting the second conductor above the first insulating member.

公开(公告)号：US20210057376A1

公开(公告)日：2021-02-25

申请号：US16816571

申请日：2020-03-12

Applicant: Kioxia Corporation

Inventor： Kazuhiro NAKANISHI ,  Shigehiro YAMAKITA ,  Kazuhiro NOJIMA ,  Kenichi KADOTA

IPC: H01L23/00

Abstract: In one embodiment, a semiconductor device includes a substrate, a lower pad provided above the substrate, and an upper pad provided on the lower pad. The lower pad includes a first pad and a plurality of first connection portions provided on the first pad, and the upper pad is provided on the plurality of first connection portions, or the upper pad includes a second pad and a plurality of second connection portions provided under the second pad, and the lower pad is provided under the plurality of second connection portions.

公开(公告)号：US20230298633A1

公开(公告)日：2023-09-21

申请号：US17894795

申请日：2022-08-24

Applicant: KIOXIA CORPORATION

Inventor： Kazuhiro NOJIMA

IPC: G11C5/06 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C5/06 ,  G11C16/0483 ,  G11C16/08

Abstract: According to one embodiment, a device includes a memory cell array that includes a plurality of memory cells connected to a plurality of pieces of gate wiring, and a test control circuit that includes a plurality of control units connected to the plurality of pieces of gate wiring. The control units each includes a transistor that includes a gate connected to a first node, one end connected to the corresponding gate wiring and another end connected to a second node, and a load unit connected between the first node and the second node. When the gate wiring is being discharged, the transistor is turned on. The gate wiring is connected to the second node via the transistor in an on state. After the gate wiring is discharged, the load unit discharges the first node.

公开(公告)号：US20220093176A1

公开(公告)日：2022-03-24

申请号：US17349501

申请日：2021-06-16

Applicant: Kioxia Corporation

Inventor： Kazuhiro NOJIMA ,  Kohei YUKI

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L23/528

Abstract: According to one embodiment, a semiconductor memory device includes a stacked layer body including conductive and insulating layers alternately stacked in a first direction, partition structures each extending in first and second directions in the stacked layer body, and an intermediate structure extending from an upper end and terminating at a position between upper and lower ends of the stacked layer body between adjacent partition structures. The partition structures include a first partition structure including first and second portions arranged in the second direction, the first portion extends from the upper end to the lower end, and the second portion is located between adjacent first portions, extends from the upper end and terminates at the position between the upper and lower ends.

公开(公告)号：US20240210334A1

公开(公告)日：2024-06-27

申请号：US18600451

申请日：2024-03-08

Applicant: Kioxia Corporation

Inventor： Yuki ABE ,  Akira HAMAGUCHI ,  Takaki HASHIMOTO ,  Kazuhiro NOJIMA ,  Kaori FUMITA

IPC: G01N23/201 ,  G01N21/47 ,  G01N21/95 ,  G01N23/207

CPC classification number: G01N23/201 ,  G01N21/4788 ,  G01N21/9501 ,  G01N23/207

Abstract: A measurement device includes: an X-ray irradiation section; an X-ray detection section configured to detect scattered X-rays generated from an object; and an analysis section configured to analyze diffraction images obtained through photoelectric conversion of the scattered X-rays and estimate a three-dimensional shape of the object. A recessed portion is formed in a first film from an opening portion in a second film formed on the first film. The analysis section estimates a three-dimensional shape of the object on the basis of the diffraction images acquired while an irradiation angle of the X-rays with respect to the object is changed and shape data obtained by measuring the object in advance. The shape data include a film thickness of the second film, a neck diameter, and a bottom diameter.

公开(公告)号：US20220262744A1

公开(公告)日：2022-08-18

申请号：US17411238

申请日：2021-08-25

Applicant: Kioxia Corporation

Inventor： Mitsunori MASAKI ,  Hisashi KATO ,  Kazuhiro NOJIMA ,  Shoichi MIYAZAKI ,  Akira YOTSUMOTO ,  Kanako SHIGA ,  Yu HIROTSU ,  Osamu MATSUURA

IPC: H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: Semiconductor memory device includes: a first and second member each extending in a first direction in a boundary part between a first and second block region and arranged in the first direction; a support pillar arranged between the first and second member at the boundary part; conductive layers separated from one another and arranged in a third direction and split by the first and second member, and the support pillar into a first and second portion; and a memory pillar penetrating through the conductive layers. The support pillar includes a lower and upper pillar. A side face of the lower pillar and an extension of a side face of the upper pillar are displaced from each other in a plane based on a second and the third direction.

公开(公告)号：US20250087502A1

公开(公告)日：2025-03-13

申请号：US18806049

申请日：2024-08-15

Applicant: Kioxia Corporation

Inventor： Kohei YUKI ,  Kazuhiro NOJIMA ,  Keiichi NIWA ,  Takanobu ONO

IPC: H01L21/67 ,  H01L21/677 ,  H01L21/78

Abstract: A semiconductor manufacturing apparatus includes a storage device configured to store first location information of a plurality of first lines on a first surface of a semiconductor wafer to be cut, and further store second location information of a second line not to be cut among the plurality of first lines; and a cutter configured to cut the semiconductor wafer along one or more of the plurality of first lines other than the second line. The semiconductor wafer is configured to be cut into a plurality of semiconductor chips.

公开(公告)号：US20230284390A1

公开(公告)日：2023-09-07

申请号：US18079514

申请日：2022-12-12

Applicant: Kioxia Corporation

Inventor： Kazuya NAGASAWA ,  Norihiro ISHII ,  Kazuhiro NOJIMA ,  Tamotsu FUJIMAKI

IPC: H05K1/18

CPC classification number: H05K1/182 ,  H05K2201/10159

Abstract: A semiconductor storage device according to an embodiment includes a board, an electronic component, and a holder. The board has a first surface. The electronic component includes a component main body and a first lead. The component main body is at a position out of the board in a direction parallel to the first surface. The first lead protrudes from the component main body toward the board. The holder is on the board. The holder holds the first lead.

公开(公告)号：US20220068804A1

公开(公告)日：2022-03-03

申请号：US17188423

申请日：2021-03-01

Applicant: KIOXIA CORPORATION

Inventor： Hideto TAKEKIDA ,  Shotaro KUZUKAWA ,  Kazuhiro NOJIMA

IPC: H01L23/522 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor storage device includes a substrate and a memory cell array. The memory cell array is above the substrate in a first direction. The memory cell array includes first to third regions arranged in a second direction. The memory cell array comprises a first stack in the first and third regions, first and second semiconductor layers extending through the first stack in the first and third regions, respectively, a second stack in the second region, a first contact extending through the second stack, a fourth insulating layer extending in the first and second directions in the second region, and a fifth insulating layer extending in the first direction and a third direction in the second region. A distance from a bottom end of the fourth insulating layer to the substrate is different from a distance from a bottom end of the fifth insulating layer to the substrate.

公开(公告)号：US20220020681A1

公开(公告)日：2022-01-20

申请号：US17145521

申请日：2021-01-11

Applicant: Kioxia Corporation

Inventor： Kazuhiro NOJIMA ,  Genki KAWAGUCHI

IPC: H01L23/528 ,  H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor memory device according to an embodiment includes a substrate. The substrate includes first and second areas, and block areas. The second area includes subareas. Each of the subareas includes a contact area and an insulating area arranged in the first direction. The contact area includes terraced portions and first contacts corresponding to two block areas. The insulating area includes second contacts corresponding to the two block areas. Contact areas of odd-numbered subareas and insulating areas of even-numbered subareas are disposed in an alternating manner in the second direction. Insulating areas of the odd-numbered subareas and contact areas of the even-numbered subareas are disposed in an alternating manner in the second direction.