公开(公告)号：US20230309311A1

公开(公告)日：2023-09-28

申请号：US17939344

申请日：2022-09-07

Applicant: Kioxia Corporation

Inventor： Keiji HOSOTANI ,  Fumitaka ARAI ,  Hiroaki KOSAKO ,  Takayuki KAKEGAWA ,  Shinya NAITO ,  Ryo FUKUOKA ,  Kouji MATSUO

IPC: H01L27/11573 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14

CPC classification number: H01L27/11573 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/14

Abstract: A semiconductor memory device includes a memory cell array and a peripheral circuit. The peripheral circuit includes a plurality of first nodes disposed corresponding to a plurality of first via electrodes, a charging circuit that charges the plurality of first nodes, a discharging circuit that discharges the plurality of first nodes, an address select circuit that electrically conducts one of the plurality of first nodes with the charging circuit or the discharging circuit in response to an input address signal, a plurality of first transistors each disposed in a current path between two of the plurality of first nodes, and a plurality of amplifier circuits that are disposed corresponding to the plurality of first via electrodes and include input terminals connected to any of the plurality of first nodes and output terminals connected to any of the plurality of first via electrodes.

公开(公告)号：US20220352188A1

公开(公告)日：2022-11-03

申请号：US17692920

申请日：2022-03-11

Applicant: Kioxia Corporation

Inventor： Ryo FUKUOKA ,  Fumitaka ARAI ,  Kouji MATSUO ,  Hiroaki KOSAKO ,  Keiji HOSOTANI ,  Takayuki KAKEGAWA ,  Shinya NAITO ,  Shinji MORI

IPC: H01L27/11519 ,  H01L27/11556 ,  G11C16/26

Abstract: A semiconductor memory device includes a first semiconductor layer, first conductive layers, electric charge accumulating portions, a first conductivity-typed second semiconductor layer, a first wiring, a second conductivity-typed third semiconductor layer, and a second conductive layer. The first semiconductor layer extends in a first direction. First conductive layers are arranged in the first direction and extend in a second direction. Electric charge accumulating portions are disposed between the first semiconductor layer and first conductive layers. The second semiconductor layer is connected to one end of the first semiconductor layer. The first wiring is connected to the first semiconductor layer via the second semiconductor layer. The third semiconductor layer is connected to a side surface in a third direction of the first semiconductor layer. The second conductive layer extends in the second direction and is connected to the first semiconductor layer via the third semiconductor layer.