公开(公告)号：US20240421071A1

公开(公告)日：2024-12-19

申请号：US18743245

申请日：2024-06-14

Applicant: Kioxia Corporation

Inventor： Ha HOANG ,  Kazuhiro MATSUO ,  Mutsumi OKAJIMA ,  Takamitsu OCHI ,  Tsuyoshi SUGISAKI ,  Isamu UJIIE

IPC: H01L23/522 ,  G11C5/06 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor memory device includes a plurality of memory layers arranged in a first direction, a first via-wiring extending in the first direction, a second via-wiring in a position different from a position of the first via-wiring in a second direction and extending in the first direction. One of the plurality of memory layers includes a first wiring disposed between the first and the second via-wiring and extending in a third direction, a first semiconductor layer electrically connected to the first via-wiring, a first gate electrode opposed to the first semiconductor layer and electrically connected to the first wiring, a first memory portion electrically connected to the first semiconductor layer, a second semiconductor layer electrically connected to the second via-wiring, a second gate electrode opposed to the second semiconductor layer and electrically connected to the first wiring, and a second memory portion electrically connected to the second semiconductor layer.

公开(公告)号：US20210257383A1

公开(公告)日：2021-08-19

申请号：US17010181

申请日：2020-09-02

Applicant: Kioxia Corporation

Inventor： Takamitsu OCHI ,  Shunsuke KASASHIMA

IPC: H01L27/11582

Abstract: A device includes conductor layers and a first pillar, extending through the conductor layers, that includes a first columnar portion, a second columnar portion, and a middle portion between the first and second columnar portions. A diameter of the middle portion is larger than a diameter of the first columnar portion and larger than a diameter of the second columnar portion. The first columnar portion includes a first semiconductor layer and a first charge storage layer. The second columnar portion includes a second semiconductor layer and a second charge storage layer. The middle portion includes a third semiconductor layer. The first and second semiconductor layers are in contact with the third semiconductor layer on a first side and a second side of the third semiconductor layer, respectively. The first charge storage layer is spaced from the second charge storage layer.