公开(公告)号：US20240324169A1

公开(公告)日：2024-09-26

申请号：US18601832

申请日：2024-03-11

Applicant: Kioxia Corporation

Inventor： Reiko SUMI ,  Takashi INUKAI ,  Tsuneo INABA ,  Takayuki MIYAZAKI

IPC: H10B12/00 ,  H01L23/482 ,  H01L23/538

CPC classification number: H10B12/0335 ,  H01L23/4824 ,  H01L23/538 ,  H10B12/485 ,  H10B12/488

Abstract: According to one embodiment, a memory device includes, a memory cell array including first to fourth sub-arrays, a first bit line coupled to the first sub-array and the second sub-array, a second bit line arranged side by side with the first bit line in a first direction and coupled to the third sub-array and the fourth sub-array, a third bit line arranged at a position different from the first bit line in a second direction and coupled to at least the second sub-array and the third sub-array, a fourth bit line arranged side by side with the third bit line in the first direction and coupled to the fourth sub-array, a first circuit electrically coupled to the first bit line and the second bit line, and a second circuit electrically coupled to the third bit line and the fourth bit line.

公开(公告)号：US20240282359A1

公开(公告)日：2024-08-22

申请号：US18582433

申请日：2024-02-20

Applicant: Kioxia Corporation

Inventor： Takeshi AOKI ,  Masaharu WADA ,  Takayuki MIYAZAKI ,  Takashi INUKAI

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C11/4087 ,  G11C11/4091 ,  G11C11/4096

Abstract: A memory includes a cell array including first and second sub arrays including memory cells and simultaneously driven in a read or a write operation. First lines are connected to the cells corresponding to one of physical rows, where the physical row is the cells arranged in a first direction in the cell array. Second lines are connected to the cells arranged in a second direction intersecting with the first direction in the cell array. A decoder selects a selection line from among the first lines in accordance with a logical row address corresponding to each of the physical rows and applies a read voltage or a write voltage to the selection line. A sense amplifier detects data from the second lines. Logical row addresses corresponding to physical rows adjacent to a certain physical row among the physical rows differ between the first sub array and the second sub array.

公开(公告)号：US20240057314A1

公开(公告)日：2024-02-15

申请号：US18448703

申请日：2023-08-11

Applicant: Kioxia Corporation

Inventor： Takeshi AOKI ,  Takayuki MIYAZAKI ,  Masaharu WADA ,  Takashi INUKAI

IPC: H10B12/00 ,  H01L29/786

CPC classification number: H10B12/33 ,  H01L29/7869 ,  H01L29/78642 ,  H10B12/48

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate and a capacitor that includes a first electrode extending in a first direction intersecting the semiconductor substrate and a second electrode facing the first electrode. A first conductive layer is above the capacitor and extends in a second direction. A semiconductor layer penetrates the first conductive layer in the first direction. A first conductor can be above or below the first conductive layer and electrically connected to the first conductive layer. A first insulating film is between the first conductive layer and the semiconductor layer. A second conductive layer extends in the second direction and is electrically connected to the first conductive layer via the first conductor.