公开(公告)号：US20240324169A1

公开(公告)日：2024-09-26

申请号：US18601832

申请日：2024-03-11

Applicant: Kioxia Corporation

Inventor： Reiko SUMI ,  Takashi INUKAI ,  Tsuneo INABA ,  Takayuki MIYAZAKI

IPC: H10B12/00 ,  H01L23/482 ,  H01L23/538

CPC classification number: H10B12/0335 ,  H01L23/4824 ,  H01L23/538 ,  H10B12/485 ,  H10B12/488

Abstract: According to one embodiment, a memory device includes, a memory cell array including first to fourth sub-arrays, a first bit line coupled to the first sub-array and the second sub-array, a second bit line arranged side by side with the first bit line in a first direction and coupled to the third sub-array and the fourth sub-array, a third bit line arranged at a position different from the first bit line in a second direction and coupled to at least the second sub-array and the third sub-array, a fourth bit line arranged side by side with the third bit line in the first direction and coupled to the fourth sub-array, a first circuit electrically coupled to the first bit line and the second bit line, and a second circuit electrically coupled to the third bit line and the fourth bit line.

公开(公告)号：US20240266258A1

公开(公告)日：2024-08-08

申请号：US18636274

申请日：2024-04-16

Applicant: ROHM CO., LTD.

Inventor： Kentaro CHIKAMATSU

IPC: H01L23/482 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L23/4824 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786

Abstract: A semiconductor device is provided with: a source wiring electrically coupled to the source electrode of a transistor; a drain wiring electrically coupled to the drain electrode of the transistor; a source pad electrically coupled to the source wiring; and, a drain pad electrically coupled to the drain wiring. The source wiring includes a first source wiring section and a second source wiring section having a width greater than that of the first source wiring section. The drain wiring includes a first drain wiring section and a second drain wiring section having a width greater than that of the first drain wiring section. The source pad at least partially overlaps the second drain wiring section in plan view. The drain pad at least partially overlaps the second source wiring section in plan view.

公开(公告)号：US20240113044A1

公开(公告)日：2024-04-04

申请号：US18538093

申请日：2023-12-13

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Yi-Feng Chang

IPC: H01L23/60 ,  H01L23/482

CPC classification number: H01L23/60 ,  H01L23/4824 ,  H01L23/522

Abstract: A semiconductor device includes a substrate and a metallization layer. The substrate has an active region that includes opposite first and second edges. The metallization layer is disposed above the substrate, and includes a pair of metal lines and a metal plate. The metal lines extend from an outer periphery of the active region into the active region and toward the second edge of the active region. The metal plate interconnects the metal lines and at least a portion of which is disposed at the outer periphery of the active region.

公开(公告)号：US20240071844A1

公开(公告)日：2024-02-29

申请号：US18155769

申请日：2023-01-18

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yizhi ZENG

IPC: H01L21/66 ,  H01L23/482

CPC classification number: H01L22/32 ,  H01L23/4824

Abstract: Embodiments relate to the field of semiconductor, and disclose a semiconductor device layout structure, a method for forming the same, and a test system. The semiconductor device layout structure includes: an active layout layer including active pattern regions arranged along a first direction; device layout sublayers, where each of the device layout sublayer includes a gate pattern region; and a plurality of contact plug sets, where each of the contact plug sets includes a source contact plug and a drain contact plug. Along the first direction, in adjacent two gate pattern regions of the device layout sublayers, a pitch between the latter gate pattern region and the corresponding source contact plug and/or the drain contact plug and a pitch between the former gate pattern region and the corresponding source contact plug and/or the drain contact plug form an arithmetic progression.

公开(公告)号：US20230369174A1

公开(公告)日：2023-11-16

申请号：US18166025

申请日：2023-02-08

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Miaomiao CHEN

IPC: H01L23/482 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/4824 ,  H01L23/5283 ,  H01L24/46 ,  H01L2224/46 ,  H01L2924/1011

Abstract: Provided is a semiconductor structure, configured to form a pad, including a substrate, a top-layer conductive line, N layers of secondary-top-layer conductive lines and a plurality of dielectric layers, N being an integer greater than or equal to 2. The top-layer conductive line and the N layers of the secondary-top-layer conductive lines are arranged above the substrate. The N layers of the secondary-top-layer conductive lines are arranged on a side of the top-layer conductive line close to the substrate. Each of the plurality of dielectric layers is located between two respective adjacent layers of the secondary-top-layer conductive lines in a vertical direction. For the N layers of the secondary-top-layer conductive lines, an area in which projections of any two layers of the secondary-top-layer conductive lines on a top surface of the substrate overlap with each other is less than a first threshold.

公开(公告)号：US11776883B2

公开(公告)日：2023-10-03

申请号：US17728220

申请日：2022-04-25

Applicant: GaN Systems Inc.

Inventor： Cameron McKnight-MacNeil ,  Greg P. Klowak

IPC: H01L23/495 ,  H01L23/482 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L29/20 ,  H01L29/778 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/18 ,  H01L29/2003 ,  H01L29/778 ,  H01L2224/04105 ,  H01L2224/82 ,  H01L2924/13091

Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. A dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, forms an external surface of the package covering underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ≥100V wherein the package body has a laminated structure configured for high voltage, high temperature operation with improved reliability.

公开(公告)号：US20230290878A1

公开(公告)日：2023-09-14

申请号：US18248344

申请日：2022-07-21

Applicant: Nuvoton Technology Corporation Japan

Inventor： Masahide TAGUCHI ,  Eiji YASUDA

IPC: H01L29/78 ,  H01L29/423 ,  H01L23/482

CPC classification number: H01L29/7813 ,  H01L29/4238 ,  H01L23/4824

Abstract: A semiconductor device includes: a semiconductor layer in a rectangular shape in a plan view; a transistor provided in a first region; and a drain lead-out region provided in a second region. A border line is a straight line parallel to longer sides of the semiconductor layer. The first region includes a plurality of source pads and gate pads. The second region includes a plurality of drain pads. One gate pad among the gate pads is disposed to dispose none of the plurality of source pads between (i) the one gate pad and (ii) one longer side and one shorter side. One drain pad among the plurality of drain pads is in the same shape as the one gate pad and is disposed close to a second vertex. The plurality of source pads include a source pad that is in a rectangular shape or an obround shape having a longitudinal direction parallel to the longer sides of the semiconductor layer.

公开(公告)号：US20230215764A1

公开(公告)日：2023-07-06

申请号：US18147957

申请日：2022-12-29

Applicant: NEXPERIA B.V.

Inventor： Rainer Mintzlaff ,  Hans-Martin Ritter

IPC: H01L21/768 ,  H01L21/3205 ,  H01L23/482 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/76895 ,  H01L21/32051 ,  H01L23/4824 ,  H01L29/49 ,  H01L29/66106 ,  H01L29/66113

Abstract: A semiconductor device including an interconnect. The interconnect is arranged to transfer current from one terminal to another, and the interconnect includes a first layer including a plurality of interweaved fingers, and each of the interweaved fingers varies in width in a direction of propagation current thereby resulting in a difference of resistance within each of the interweaved fingers in the direction of propagation of current; a second layer arranged below the first layer. The second layer compensates for the difference of resistance in the first layer.

公开(公告)号：US11658235B2

公开(公告)日：2023-05-23

申请号：US15901171

申请日：2018-02-21

Applicant: Kabushiki Kaisha Toshiba

Inventor： Masahiko Kuraguchi ,  Yosuke Kajiwara ,  Miki Yumoto ,  Hiroshi Ono

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L23/528 ,  H01L23/522 ,  H01L29/417 ,  H01L23/482 ,  H01L29/45 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5286 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/452

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first region, and a first insulating layer. The first electrode includes a first electrode portion. The first region contains Ga and N. The first region includes a first subregion, a second subregion, and a third subregion. The first subregion and the third subregion contain at least one first element selected from the group consisting of Ar, B, P, N, and Fe. The first subregion is located between the first electrode portion and the second subregion in a first direction. The second subregion does not contain the first element, or concentration of the first element in the second subregion is lower than concentration of the first element in the first subregion and lower than concentration of the first element in the third subregion. The first insulating layer is provided between the first electrode and the first region.

公开(公告)号：US20190214489A1

公开(公告)日：2019-07-11

申请号：US16355172

申请日：2019-03-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji SASAKI ,  Kingo KUROTANI ,  Takashi KITAHARA

IPC: H01L29/737 ,  H03F3/19 ,  H01L23/535 ,  H01L29/417 ,  H01L29/06 ,  H01L27/082 ,  H01L23/00 ,  H01L23/482 ,  H01L29/40

CPC classification number: H01L29/7371 ,  H01L23/4824 ,  H01L23/535 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L27/0823 ,  H01L29/0692 ,  H01L29/40 ,  H01L29/41708 ,  H01L2224/0401 ,  H01L2224/13013 ,  H01L2224/1302 ,  H01L2224/16227 ,  H01L2924/13051 ,  H03F3/19 ,  H03F2200/408 ,  H03F2200/451 ,  H01L2924/00012

Abstract: A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.