Storage device and storage system

    公开(公告)号:US11972110B2

    公开(公告)日:2024-04-30

    申请号:US17931363

    申请日:2022-09-12

    CPC classification number: G06F3/0613 G06F3/0659 G06F3/0679

    Abstract: According to one embodiment, in response to receiving, from a host, one or more second type commands, a controller of the storage device maintains the received one or more second type commands in a memory region in the storage device without completing processing of the received one or more second type commands. In response to receiving the first type command from the host, the controller completes processing of a second type command, and transmits a command completion response for the first type command to the host as a first preceding response for the first type command. In response to completion of processing of the first type command, the controller transmits a command completion response for the first type command to the host.

    Method of controlling nonvolatile memory by managing block groups

    公开(公告)号:US12045514B2

    公开(公告)日:2024-07-23

    申请号:US18305794

    申请日:2023-04-24

    Abstract: According to one embodiment, a memory system writes first write data into each non-defective physical block belonging to a first write destination block group. The memory system notifies a host of a first identifier of the first write data, an address specifying the first write destination block group, a first offset indicating a top write destination physical storage location in the first write destination block group in which the first write data is written, length of the first write data, and first bitmap information including a plurality of bits, each of the bits corresponding to each of physical blocks belonging to the first write destination block group and indicating whether or not the corresponding physical block is a defective block.

    Information processing apparatus and cache control method

    公开(公告)号:USRE49418E1

    公开(公告)日:2023-02-14

    申请号:US16209330

    申请日:2018-12-04

    Abstract: According to one embodiment, an information processing apparatus includes a storage device, a volatile memory, and a processor. The storage device includes a controller, a first nonvolatile storage module, and a second nonvolatile storage module whose access speed is higher than an access speed of the first nonvolatile storage module. The processor is configured to execute an operating system and a cache driver that are loaded into the volatile memory. The cache driver uses at least part of an area in the second nonvolatile storage module as a cache for the first nonvolatile storage module.

    Information processing apparatus and cache control method

    公开(公告)号:USRE49417E1

    公开(公告)日:2023-02-14

    申请号:US15073618

    申请日:2016-03-17

    Abstract: According to one embodiment, an information processing apparatus includes a storage device, a volatile memory, and a processor. The storage device includes a controller, a first nonvolatile storage module, and a second nonvolatile storage module whose access speed is higher than an access speed of the first nonvolatile storage module. The processor is configured to execute an operating system and a cache driver that are loaded into the volatile memory. The cache driver uses at least part of an area in the second nonvolatile storage module as a cache for the first nonvolatile storage module.

    Information processing method in a multi-level hierarchical memory system

    公开(公告)号:USRE49818E1

    公开(公告)日:2024-01-30

    申请号:US16939224

    申请日:2020-07-27

    CPC classification number: G06F12/0866 Y02D10/00

    Abstract: According to one embodiment, an information processing apparatus includes a memory includes a buffer area, a first storage, a second storage and a driver. The buffer area is reserved in order to transfer data between the driver and a host system that requests for data writing and data reading. The driver is configured to write data into the second storage and read data from the second storage in units of predetermined blocks using the first storage as a cache for the second storage. The driver is further configured to reserve a cache area in the memory, between the buffer area and the first external storage, and between the buffer area and the second storage. The driver is further configured to manage the cache area in units of the predetermined blocks.

    Memory including a plurality of nonvolatile memory dies each including a plurality of physical blocks

    公开(公告)号:US11366612B2

    公开(公告)日:2022-06-21

    申请号:US16815594

    申请日:2020-03-11

    Abstract: According to one embodiment, a memory system writes first write data into each non-defective physical block belonging to a first write destination block group. The memory system notifies a host of a first identifier of the first write data, an address specifying the first write destination block group, a first offset indicating a top write destination physical storage location in the first write destination block group in which the first write data is written, length of the first write data, and first bitmap information including a plurality of bits, each of the bits corresponding to each of physical blocks belonging to the first write destination block group and indicating whether or not the corresponding physical block is a defective block.

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