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公开(公告)号:US12236106B2
公开(公告)日:2025-02-25
申请号:US17941388
申请日:2022-09-09
Applicant: Kioxia Corporation
Inventor: Shinichi Kanno , Yuki Sasaki
IPC: G06F3/06
Abstract: According to one embodiment, a controller of a memory system writes, in response to receiving from the host a write command specifying a logical address, data received from the host to a first write destination block. The controller manages a first list and first storage location information, the first list including a plurality of logical addresses corresponding respectively to write-uncompleted data, and the first storage location information indicating a storage location at a beginning of a write-uncompleted region in the first write destination block. In a case where a power loss has occurred without notice from the host, the controller writes the first list and the first storage location information to the nonvolatile memory using power from a capacitor.
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公开(公告)号:US12229448B2
公开(公告)日:2025-02-18
申请号:US18449924
申请日:2023-08-15
Applicant: KIOXIA CORPORATION
Inventor: Shinichi Kanno
IPC: G06F3/06
Abstract: According to one embodiment, a controller of a memory system executes a first write operation of writing write data into a first storage region, in response to reception of one or more write requests for specifying a first zone from a host, during a period from execution of an erase operation of the first storage region until a first time elapses. When the first time has elapsed after execution of the erase operation, in a state in which an unwritten region having a size larger than or equal to a first size remains in the first storage region, the controller does not execute the first write operation, allocates the first storage region as a nonvolatile buffer capable of temporarily storing write data to be written to each of a plurality of zones.
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公开(公告)号:US12222857B2
公开(公告)日:2025-02-11
申请号:US18457672
申请日:2023-08-29
Applicant: KIOXIA CORPORATION
Inventor: Yuki Sasaki , Shinichi Kanno , Takahiro Kurita
IPC: G06F12/02 , G06F12/1009
Abstract: According to one embodiment, a memory system includes a non-volatile memory and a data map configured to manage validity of data written in the non-volatile memory. The data map includes a plurality of first fragment tables corresponding to a first hierarchy and a second fragment table corresponding to a second hierarchy higher than the first hierarchy. Each of the first fragment tables is used to manage the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second fragment table is used for each of the first fragment tables to manage reference destination information for referencing the first fragment table.
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公开(公告)号:US12147333B2
公开(公告)日:2024-11-19
申请号:US18303863
申请日:2023-04-20
Applicant: KIOXIA CORPORATION
Inventor: Shinichi Kanno , Naoki Esaka
IPC: G06F12/02 , G06F12/08 , G06F12/0868 , G06F12/0871 , G06F13/16 , G06F13/40
Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.
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公开(公告)号:US12135903B2
公开(公告)日:2024-11-05
申请号:US18347905
申请日:2023-07-06
Applicant: KIOXIA CORPORATION
Inventor: Shinichi Kanno
IPC: G06F3/06
Abstract: According to one embodiment, a memory system manages a plurality of first weights that correspond to the plurality of queues, and a plurality of second weights that correspond to the plurality of queues. The memory system selects a queue of a largest or smallest second weight, of the plurality of queues, as a queue of a highest priority, and starts execution of a command stored in the selected queue. The memory system updates the second weight corresponding to the selected queue by subtracting the first weight corresponding to the selected queue from the second weight corresponding to the selected queue or by adding the first weight corresponding to the selected queue to the second weight corresponding to the selected queue.
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公开(公告)号:US12014090B2
公开(公告)日:2024-06-18
申请号:US18301694
申请日:2023-04-17
Applicant: KIOXIA CORPORATION
Inventor: Shinichi Kanno
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0656 , G06F3/0679
Abstract: According to one embodiment, a memory system determines, for each of groups corresponding to streams, whether or not a length of write data associated with a set of write commands belonging to a same group reaches a minimum write size of a nonvolatile memory. When a length of write data associated with a set of write commands belonging to a first group corresponding to a first stream reaches the minimum write size, the memory system transfers the write data associated with the set of write commands belonging to the first group from a write buffer in a memory of the host to a first buffer in the memory system, and writes the write data transferred to the first buffer to a first write destination block corresponding to the first stream.
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公开(公告)号:US11977481B2
公开(公告)日:2024-05-07
申请号:US18310597
申请日:2023-05-02
Applicant: KIOXIA CORPORATION
Inventor: Kazuhiro Fukutomi , Kenichiro Yoshii , Shinichi Kanno , Shigehiro Asano
CPC classification number: G06F12/0246 , G06F3/061 , G06F3/0631 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F12/00 , G06F12/16 , G06F3/0608 , G06F3/0611 , G06F3/0638 , G06F3/0644 , G06F3/0665 , G06F3/0688 , G06F2212/1016 , G06F2212/214 , G06F2212/7202 , G06F2212/7205
Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
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公开(公告)号:US11923325B2
公开(公告)日:2024-03-05
申请号:US17695654
申请日:2022-03-15
Applicant: Kioxia Corporation
Inventor: Yasuhito Yoshimizu , Takashi Fukushima , Tatsuro Hitomi , Arata Inoue , Masayuki Miura , Shinichi Kanno , Toshio Fujisawa , Keisuke Nakatsuka , Tomoya Sanuki
IPC: H01L23/00 , G06F11/07 , H01L23/544
CPC classification number: H01L24/05 , G06F11/073 , G06F11/0751 , H01L23/544 , H01L2223/5446 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05164 , H01L2924/14511
Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.
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公开(公告)号:US11861202B2
公开(公告)日:2024-01-02
申请号:US17468163
申请日:2021-09-07
Applicant: Kioxia Corporation
Inventor: Naoki Esaka , Shinichi Kanno
IPC: G06F3/06
CPC classification number: G06F3/0644 , G06F3/0604 , G06F3/0659 , G06F3/0679
Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a first write request associated with first data from a host. In response to a lapse of first time since the reception of the first write request, the controller starts a write process of second data to the nonvolatile memory. The second data includes at least the first data. The controller transmits a first response to the first write request to the host in response to completion of the write process. The first time is time obtained by subtracting second time from third time designated by the host as a time limit of the transmission of the first response since the reception of the first write request.
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公开(公告)号:US11853200B2
公开(公告)日:2023-12-26
申请号:US17653323
申请日:2022-03-03
Applicant: Kioxia Corporation
Inventor: Shinichi Kanno
IPC: G06F12/02 , G06F3/06 , G06F12/0891
CPC classification number: G06F12/0246 , G06F3/0604 , G06F3/0652 , G06F3/0679 , G06F12/0253 , G06F12/0292 , G06F12/0891 , G06F2212/7201 , G06F2212/7205 , G06F2212/7209
Abstract: According to one embodiment, a controller writes a first data associated with a write request and a first logical address specified by the write request to a first block. The controller updates a logical-to-physical address translation table such that a first physical address indicating a first storage location in the first block in which the first data is written is associated with the first logical address. In response to receiving an invalidation request for invalidating the first data corresponding to the first logical address, the controller acquires, from the logical-to-physical address translation table, the first physical address, and updates a valid data identifier corresponding to a storage location indicated by the first physical address to a value indicating invalidation.
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