公开(公告)号：US12300328B2

公开(公告)日：2025-05-13

申请号：US18177877

申请日：2023-03-03

Applicant: Kioxia Corporation

Inventor： Masahiro Saito ,  Kiwamu Watanabe ,  Yuko Noda ,  Tsukasa Tokutomi ,  Yoshiki Takai

IPC: G11C7/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: A memory controller receives first, second, and third data by first, second, and third reads, specifying a first address, and respectively specifying first, second, and third read voltages higher in this order. The controller instructs a memory to execute a fourth read specifying a fourth read voltage lower than the first read voltage and the first address when a first difference between a first-value-bit count of the first data and an expected value is smaller than a second difference between a first-value-bit count of the third data and the expected value. The memory controller instructs the memory to execute a fifth read specifying a fifth read voltage higher than the third read voltage and the first address when the first difference is larger than the second difference.