公开(公告)号：US11929292B2

公开(公告)日：2024-03-12

申请号：US17503947

申请日：2021-10-18

申请人： Kioxia Corporation

发明人： Naoki Yamamoto ,  Yu Hirotsu

IPC分类号： H01L21/66 ,  H01L21/768 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

CPC分类号： H01L22/30 ,  H01L21/76816 ,  H01L22/12 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

摘要： A semiconductor memory according to an embodiment includes first and second areas, an active region, a non-active region, a first stacked body, a plurality of first pillars, a first contact, a second stacked body, and a second contact. The active region includes part of each of the first and second areas. The non-active region includes part of each of the first and second areas. The second stacked body is in the non-active region. The second stacked body includes second insulators and second conductors which are alternately stacked. A second contact is in contact with a second conductor in a first interconnect layer and a second conductor in a second interconnect layer.

公开(公告)号：US11594549B2

公开(公告)日：2023-02-28

申请号：US17202690

申请日：2021-03-16

申请人： Kioxia Corporation

发明人： Ayumi Watarai ,  Taichi Iwasaki ,  Osamu Matsuura ,  Yu Hirotsu ,  Sota Matsumoto

IPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  G11C8/14 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11551

摘要： A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, an outer peripheral conductive layer, a lower layer conductive layer, and a first contact. The substrate includes a core region and a first region.
The outer peripheral conductive layer is provided to surround the core region in the first region. The outer peripheral conductive layer is included in a first layer. The lower layer conductive layer is provided in the first region. The first contact is provided on the lower layer conductive layer to surround the core region in the first region. An upper end of the first contact is included in the first layer. The first contact is electrically connected to the outer peripheral conductive layer.