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    Power controlling method for semiconductor storage device and semiconductor storage device employing same
    1.
    发明授权
    Power controlling method for semiconductor storage device and semiconductor storage device employing same 有权
    半导体存储装置的功率控制方法及采用该半导体存储装置的半导体存储装置

    公开(公告)号：US06795362B2

    公开(公告)日：2004-09-21

    申请号：US10227950

    申请日：2002-08-27

    申请人： Kiyoshi Nakai ,  Yutaka Ito ,  Takeshi Hashimoto ,  Hideaki Kato

    发明人： Kiyoshi Nakai ,  Yutaka Ito ,  Takeshi Hashimoto ,  Hideaki Kato

    IPC分类号： G11C700

    CPC分类号： G11C7/1018 ,  G11C11/406 ,  G11C2207/2227

    摘要： A method for controlling power for a semiconductor storage device and the semiconductor storage device are provided which enable power consumption to be greatly reduced in a standby state. The power control method uses an ultra-low power consumption mode in which power control can be exerted in the standby state. In the ultra-low power consumption mode, a burst self-refresh state, power-OFF state, and power-ON state are provided. In the burst self-refresh state, memory cells are refreshed in a centralized manner. In the power-OFF state, an internal power source circuit can be partially turned OFF. In the power-ON state, internal power sources having been partially turned OFF are turned ON. Therefore, it is possible to greatly reduce power consumption in the standby state.

    摘要翻译： 提供了一种用于控制半导体存储装置和半导体存储装置的电力的方法，其在待机状态下能够大大降低功耗。 功率控制方法使用能够在待机状态下进行功率控制的超低功耗模式。 在超低功耗模式中，提供突发自刷新状态，断电状态和通电状态。 在突发自刷新状态下，以集中方式刷新存储单元。 在断电状态下，内部电源电路可以部分地断开。 在通电状态下，部分断开的内部电源被接通。 因此，可以大大降低待机状态下的功耗。

    Semiconductor memory device and refresh period controlling method
    2.
    发明申请
    Semiconductor memory device and refresh period controlling method 审中-公开
    半导体存储器件和刷新周期控制方法

    公开(公告)号：US20090193301A1

    公开(公告)日：2009-07-30

    申请号：US12318840

    申请日：2009-01-09

    申请人： Yutaka Ito ,  Takeshi Hashimoto

    发明人： Yutaka Ito ,  Takeshi Hashimoto

    IPC分类号： H03M13/05 ,  G06F11/00 ,  G06F11/07

    CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4062

    摘要： Disclosed is a memory device including an error rate measurement circuit and a control circuit. The error rate measurement circuit, carrying a BIST circuit, reads out and writes data for an area for monitor bits every refresh period to detect an error rate (error count) with the refresh period. The control circuit performs control for elongating and shortening the refresh period so that a desired error rate will be achieved. The BIST circuit issues an internal command and an internal address and drives the DRAM from inside. The BIST circuit writes and reads out desired data, compares the monitor bits to expected values (error decision) and counts the errors.

    摘要翻译： 公开了一种包括错误率测量电路和控制电路的存储器件。 携带BIST电路的误差率测量电路每刷新周期读出并写入用于监视位的区域的数据，以检测刷新周期的错误率（错误计数）。 控制电路进行用于延长和缩短刷新周期的控制，从而实现期望的误码率。 BIST电路发出内部命令和内部地址，并从内部驱动DRAM。 BIST电路写入和读出所需的数据，将监视位与预期值进行比较（错误判定），并对错误进行计数。

    Semiconductor memory device and refresh period controlling method
    3.
    发明授权
    Semiconductor memory device and refresh period controlling method 失效

    公开(公告)号：US07493531B2

    公开(公告)日：2009-02-17

    申请号：US11152762

    申请日：2005-06-15

    申请人： Yutaka Ito ,  Takeshi Hashimoto

    发明人： Yutaka Ito ,  Takeshi Hashimoto

    IPC分类号： G06F11/00 ,  H03M13/00

    CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4062

    摘要： Disclosed is a memory device including an error rate measurement circuit and a control circuit. The error rate measurement circuit, carrying a BIST circuit, reads out and writes data for an area for monitor bits every refresh period to detect an error rate (error count) with the refresh period. The control circuit performs control for elongating and shortening the refresh period so that a desired error rate will be achieved. The BIST circuit issues an internal command and an internal address and drives the DRAM from inside. The BIST circuit writes and reads out desired data, compares the monitor bits to expected values (error decision) and counts the errors.

    Booster circuit capable of switching between a conventional mode and a low consumption current mode
    4.
    发明授权
    Booster circuit capable of switching between a conventional mode and a low consumption current mode 有权
    能够在常规模式和低功耗电流模式之间切换的升压电路

    公开(公告)号：US06762639B2

    公开(公告)日：2004-07-13

    申请号：US10201553

    申请日：2002-07-23

    申请人： Yutaka Ito ,  Takeshi Hashimoto

    发明人： Yutaka Ito ,  Takeshi Hashimoto

    IPC分类号： G05F110

    CPC分类号： H02M3/07 ,  H02M2001/0032 ,  H02M2001/009 ,  Y02B70/16

    摘要： In a booster circuit comprising a first pump capacitor (CP1) connected between nodes (N1, N3) and a second pump capacitor (CP2) connected between nodes (N2, N4), the booster circuit comprises first through fifth switches (S1-S5). Connected to the node (N1), the first switch (S1) is connected to one of a power-supply node, a ground node, and a booster node. Connected to the node (N2), the second switch (S2) is connected to one of the power-supply node, the ground node, and the booster node. Disposed between the nodes (N3, N4), the third switch (S3) makes or breaks. Connected to the node (N3), the fourth switch (S4) is connected to one of the power-supply node, the booster node, and a non-connective node. Connected to the node (N4), the fifth switch (N5) is connected to one of the power-supply node, the booster node, and the non-connective node.

    摘要翻译： 在包括连接在节点（N1，N3）和连接在节点（N2，N4）之间的第二泵电容器（CP2））之间的第一泵电容器（CP1）的升压电路中，升压电路包括第一至第五开关（S1-S5） 。 连接到节点（N1），第一开关（S1）连接到电源节点，接地节点和升压节点之一。 连接到节点（N2），第二开关（S2）连接到电源节点，接地节点和升压节点之一。 在节点（N3，N4）之间，第三个交换机（S3）发生或断开。 连接到节点（N3），第四开关（S4）连接到电源节点，升压节点和非连接节点之一。 连接到节点（N4），第五交换机（N5）连接到电源节点，升压节点和非连接节点之一。

    Semiconductor memory device
    5.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20050286331A1

    公开(公告)日：2005-12-29

    申请号：US11154625

    申请日：2005-06-17

    申请人： Yutaka Ito ,  Takeshi Hashimoto ,  Eiji Yamasaki ,  Shigeo Takeuchi ,  Masayuki Kaneda

    发明人： Yutaka Ito ,  Takeshi Hashimoto ,  Eiji Yamasaki ,  Shigeo Takeuchi ,  Masayuki Kaneda

    IPC分类号： G11C7/00 ,  G11C11/406

    CPC分类号： G11C11/406 ,  G11C2211/4062 ,  G11C2211/4067

    摘要： Disclosed is a semiconductor memory device including an on-chip ECC circuit and having a data retention mode which includes, in the order of state transition, an encoding state EEST by an error correction circuit in which the error correction circuit carries out calculation of parity bits of data of the memory cells, a burst self-refresh state BSST in which the memory cells are self-refreshed in a burst with a period shorter than in ordinary self-refresh, a power-off state PFST in which an internal power supply circuit is partially turned off, a power-on state PNST in which the internal power supply circuit, partially turned off, is turned on, and a decoding state EDST by the error correction circuit in which the error correction circuit corrects errors of the memory cells. In case a command for exiting from the data retention mode in the encoding state, transition may be made to an idle state IST so that re-entry may be made from the decoding state EDST to the BSST.

    摘要翻译： 公开了一种包括片上ECC电路并且具有数据保持模式的半导体存储器件，该数据保持模式按状态转换的顺序包括纠错电路的编码状态EEST，其中纠错电路执行奇偶位的计算 的存储器单元的数据，其中存储器单元以比普通自刷新更短的周期的脉冲串自刷新的脉冲串自刷新状态BSST，电源关闭状态PFST，其中内部电源电路 内部电源电路被部分关断的通电状态PNST和通过纠错电路校正存储单元的错误的纠错电路的解码状态EDST被部分关闭。 在编码状态下从数据保持模式退出的命令的情况下，可以转换到空闲状态IST，以便可以从解码状态EDST到BSST进行重新输入。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07184351B2

    公开(公告)日：2007-02-27

    申请号：US11154625

    申请日：2005-06-17

    申请人： Yutaka Ito ,  Takeshi Hashimoto ,  Eiji Yamasaki ,  Shigeo Takeuchi ,  Masayuki Kaneda

    发明人： Yutaka Ito ,  Takeshi Hashimoto ,  Eiji Yamasaki ,  Shigeo Takeuchi ,  Masayuki Kaneda

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C2211/4062 ,  G11C2211/4067

    摘要： A semiconductor memory device including an on-chip ECC circuit and having a data retention mode which includes, in the order of state transition, an encoding state EEST by an error correction circuit in which the error correction circuit carries out calculation of parity bits of data of the memory cells, a burst self-refresh state BSST in which the memory cells are self-refreshed in a burst with a period shorter than in ordinary self-refresh, a power-off state PFST in which an internal power supply circuit is partially turned off, a power-on state PNST in which the internal power supply circuit, partially turned off, is turned on, and a decoding state EDST by the error correction circuit in which the error correction circuit corrects errors of the memory cells. In case a command for exiting from the data retention mode in the encoding state, transition may be made to an idle state IST so that re-entry may be made from the decoding state EDST to the BSST.

    摘要翻译： 一种包括片上ECC电路并具有数据保持模式的半导体存储器件，该数据保持模式按照状态转换的顺序包括纠错电路中的纠错电路的编码状态EEST，其中错误校正电路执行数据的奇偶校验位的计算 存储单元的突发自刷新状态BSST，其中存储器单元以比普通自刷新更短的周期的脉冲串进行自刷新，其中内部电源电路部分地处于断电状态PFST 关闭其中部分关闭的内部电源电路接通的上电状态PNST，以及其中纠错电路校正存储器单元的错误的纠错电路的解码状态EDST。 在编码状态下从数据保持模式退出的命令的情况下，可以转换到空闲状态IST，以便可以从解码状态EDST到BSST进行重新输入。

    Semiconductor memory device control method and semiconductor memory device
    7.
    发明授权
    Semiconductor memory device control method and semiconductor memory device 有权

    公开(公告)号：US06990031B2

    公开(公告)日：2006-01-24

    申请号：US10231794

    申请日：2002-08-29

    申请人： Takeshi Hashimoto ,  Yutaka Ito

    发明人： Takeshi Hashimoto ,  Yutaka Ito

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4074 ,  G11C11/406

    摘要： In a semiconductor memory device which requires a refresh operation, a control method stops supplying a word line voltage which is a boosted voltage higher than an external supply voltage, a memory array substrate voltage which is a negative voltage supplied to a semiconductor substrate, and a bit line precharge voltage for use in reproducing data held in memory cells for a predetermined period at the end of each refresh operation. In this event, voltage output terminals of the word line and memory array substrate voltages are respectively driven to a ground potential. For recovering these voltages, the delivery of the word line voltage is stopped until the memory array substrate voltage rises to some extent.

    Semiconductor memory device and refresh period controlling method
    8.
    发明申请
    Semiconductor memory device and refresh period controlling method 失效
    半导体存储器件和刷新周期控制方法

    公开(公告)号：US20050281112A1

    公开(公告)日：2005-12-22

    申请号：US11152762

    申请日：2005-06-15

    申请人： Yutaka Ito ,  Takeshi Hashimoto

    发明人： Yutaka Ito ,  Takeshi Hashimoto

    IPC分类号： G11C7/00 ,  G11C11/406

    CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4062

    摘要： Disclosed is a memory device including an error rate measurement circuit and a control circuit. The error rate measurement circuit, carrying a BIST circuit, reads out and writes data for an area for monitor bits every refresh period to detect an error rate (error count) with the refresh period. The control circuit performs control for elongating and shortening the refresh period so that a desired error rate will be achieved. The BIST circuit issues an internal command and an internal address and drives the DRAM from inside. The BIST circuit writes and reads out desired data, compares the monitor bits to expected values (error decision) and counts the errors.

    摘要翻译： 公开了一种包括错误率测量电路和控制电路的存储器件。 携带BIST电路的误差率测量电路每刷新周期读出并写入用于监视位的区域的数据，以检测刷新周期的错误率（错误计数）。 控制电路进行用于延长和缩短刷新周期的控制，从而实现期望的误码率。 BIST电路发出内部命令和内部地址，并从内部驱动DRAM。 BIST电路写入和读出所需的数据，将监视位与预期值进行比较（错误判定），并对错误进行计数。

    High-frequency interpolation device and high-frequency interpolation method
    9.
    发明授权
    High-frequency interpolation device and high-frequency interpolation method 有权
    高频插补装置和高频插补方法

    公开(公告)号：US08554349B2

    公开(公告)日：2013-10-08

    申请号：US12680899

    申请日：2008-10-22

    申请人： Takeshi Hashimoto

    发明人： Takeshi Hashimoto

    IPC分类号： G06F17/00 ,  H03G5/00

    CPC分类号： G10L21/038

    摘要： It is possible to generate an interpolation signal in which spectrum in frequency characteristics develops in a continuous manner according to a reproduced music without increasing the sampling rate (sampling frequency) in up-sampling processing. A high-frequency interpolation device 1 includes: a frequency band determination section 2 that determines a bandwidth type of an audio signal as a frequency band determination value preset for each bandwidth according to the frequency characteristics of the audio signal; and an interpolation signal generation section 3 that selects a filter coefficient of a high-pass filter in accordance with the frequency band determination value 2, performs filtering for the audio signal by using the high-pass filter having the selected filter coefficient, and generates a high-frequency interpolation signal for the audio signal.

    摘要翻译： 可以生成内插信号，其中频率特性中的频谱根据再现的音乐以连续的方式发展，而不增加上采样处理中的采样率（采样频率）。 高频内插装置1包括：频带确定部分2，其根据音频信号的频率特性，将音频信号的带宽类型确定为针对每个带宽预设的频带确定值; 以及根据频带判定值2选择高通滤波器的滤波器系数的插值信号生成部3，通过使用具有选择的滤波器系数的高通滤波器对音频信号进行滤波，并生成 用于音频信号的高频插值信号。