公开(公告)号：US5966110A

公开(公告)日：1999-10-12

申请号：US758207

申请日：1996-11-26

Applicant: Klaas Van Zalinge

Inventor： Klaas Van Zalinge

IPC: G09G3/14 ,  H05B33/08 ,  G09G3/32

CPC classification number: H05B33/0803 ,  G09G3/14 ,  H05B33/0818

Abstract: An LED driver drives a plurality of light emitting diodes (LEDs) having first terminals connected to a common output stage and second terminals respectively receiving different, suitably rectified, phases of a sinusoidal signal. An output stage of the LED driver includes a first bipolar transistor coupled between a first supply terminal and the first terminals of the LED's. A first MOS transistor drives the base of the first bipolar transistor. The gate of the first MOS transistor is coupled to a first reference voltage. A second bipolar cascode transistor is connected in series with the first MOS transistor and biased by a second reference voltage such that the voltage across the first MOS transistor does not exceed a limit value.

Abstract translation: LED驱动器驱动具有连接到公共输出级的第一端子和分别接收正弦信号的不同的，适当整流的相位的第二端子的多个发光二极管（LED）。 LED驱动器的输出级包括耦合在第一电源端子和LED的第一端子之间的第一双极晶体管。 第一MOS晶体管驱动第一双极晶体管的基极。 第一MOS晶体管的栅极耦合到第一参考电压。 第二双极级共源共栅晶体管与第一MOS晶体管串联连接并被第二参考电压偏置，使得第一MOS晶体管两端的电压不超过极限值。

公开(公告)号：US6124746A

公开(公告)日：2000-09-26

申请号：US124817

申请日：1998-07-29

Applicant: Klaas Van Zalinge

Inventor： Klaas Van Zalinge

IPC: H03K5/13 ,  H03K5/159 ,  H03K5/153

CPC classification number: H03K5/13

Abstract: An adjustable delay circuit, for a logic input signal, comprises circuitry for charging a capacitance at a first constant current when the logic signal switches to a first logic state; circuitry for discharging the capacitance at a second constant current when the logic signal switches to the second logic state; circuitry for stopping charging and discharging of the capacitance between the moment when the voltage across the capacitance reaches a high threshold or a low threshold and a subsequent switching of the logic signal; and a first comparator connected to switch the state of an output signal when the voltage across the capacitance crosses a third threshold included between the first and second thresholds.

Abstract translation: 用于逻辑输入信号的可调延迟电路包括用于在逻辑信号切换到第一逻辑状态时以第一恒定电流对电容进行充电的电路; 当逻辑信号切换到第二逻辑状态时，以第二恒定电流放电电容的电路; 用于在电容两端的电压达到高阈值或低阈值以及随后的逻辑信号切换的瞬间停止对电容进行充电和放电的电路; 以及第一比较器，连接成当跨越电容的电压跨越包括在第一和第二阈值之间的第三阈值时切换输出信号的状态。

公开(公告)号：US5963092A

公开(公告)日：1999-10-05

申请号：US980194

申请日：1997-11-26

Applicant: Klaas Van Zalinge

Inventor： Klaas Van Zalinge

IPC: H03F3/45 ,  H03F3/50

CPC classification number: H03F3/50 ,  H03F3/45085 ,  H03F2203/45291 ,  H03F2203/45392

Abstract: A differential transconductance amplifier includes two first NPN transistors, whose bases receive a differential input voltage, and whose collectors are coupled to a first supply voltage through two respective first current sources; two second NPN transistors respectively coupling the emitters of the first transistors to a second supply voltage, and whose bases are coupled to the collectors of the respective first transistors through level shifters; and a resistive means coupled between the emitters of the first transistors. Each level shifter includes a third PNP transistor coupled between the collector of the respective first transistor and the base of the respective second transistor, and whose control terminal receives a constant bias voltage independent of the differential input voltage.

Abstract translation: 差分跨导放大器包括两个第一NPN晶体管，其基极接收差分输入电压，并且其集电极通过两个相应的第一电流源耦合到第一电源电压; 分别将第一晶体管的发射极耦合到第二电源电压的两个第二NPN晶体管，其基极通过电平转换器耦合到相应的第一晶体管的集电极; 以及耦合在第一晶体管的发射极之间的电阻装置。 每个电平移位器包括耦合在相应的第一晶体管的集电极和相应的第二晶体管的基极之间的第三PNP晶体管，并且其控制端子接收与差分输入电压无关的恒定偏置电压。

公开(公告)号：US5757209A

公开(公告)日：1998-05-26

申请号：US573898

申请日：1995-12-18

Applicant: Klaas Van Zalinge ,  Serge Hembert

Inventor： Klaas Van Zalinge ,  Serge Hembert

IPC: H03K17/00 ,  G01R19/00 ,  H03K5/153

CPC classification number: G01R19/0038

Abstract: The present invention relates to a circuit for supplying the extremum voltage among several input voltages, including, for each input voltage, a first bipolar transistor, the base of which receives the input voltage and the emitter of which is connected to a common output supplying the extremum voltage; a first current source for biasing the emitter of the first transistor; and switching means for disconnecting the first source from the first transistor when this transistor is blocked.

Abstract translation: 本发明涉及一种用于在多个输入电压之间提供极值电压的电路，包括针对每个输入电压的第一双极晶体管，其基极接收输入电压，其发射极连接到提供 极值电压; 用于偏置第一晶体管的发射极的第一电流源; 以及用于在该晶体管被阻塞时将第一源与第一晶体管断开的开关装置。