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1.发明授权公开(公告)号：US07386064B2
公开(公告)日：2008-06-10
申请号：US10494245
申请日：2002-11-06
IPC分类号： H03D3/18
CPC分类号： H03L7/107 , H03L7/0898 , H03L7/10
摘要： In one embodiment, a PLL circuit is provided with a plurality of pull-in operation modes for pulling a voltage across a filter capacitor (C1, C2) in a lock-up voltage, and with a register (CRG) for designating one of the plurality of pull-in operation modes. The pull-in operation is performed in accordance with a setting value in the register.
摘要翻译： 在一个实施例中，PLL电路具有多个拉入操作模式，用于在锁定电压下拉过滤波电容器（C 1，C 2）上的电压，并具有用于指定一个的寄存器（CRG） 的多个拉入操作模式。 根据寄存器的设定值进行拉入动作。
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2.发明申请公开(公告)号：US20050068074A1
公开(公告)日：2005-03-31
申请号：US10494245
申请日：2002-11-06
申请人： Koichi Yahagi , Ryoji Furuya , Fumiaki Matsuzaki , Robert Henshaw
发明人： Koichi Yahagi , Ryoji Furuya , Fumiaki Matsuzaki , Robert Henshaw
CPC分类号： H03L7/107 , H03L7/0898 , H03L7/10
摘要： In one embodiment, a PLL circuit is provided with a plurality of pull-in operation modes for pulling a voltage across a filter capacitor (C1, C2) in a lock-up voltage, and with a register (CRG) for designating one of the plurality of pull-in operation modes. The pull-in operation is performed in accordance with a setting value in the register.
摘要翻译： 在一个实施例中，PLL电路具有多个拉入操作模式，用于在锁定电压中拉过滤波电容器（C1，C2）上的电压，并且具有用于指定其中之一的寄存器（CRG） 多个拉入操作模式。 根据寄存器的设定值进行拉入动作。
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公开(公告)号：US07848716B2
公开(公告)日：2010-12-07
申请号：US11360424
申请日：2006-02-24
申请人： Ryoji Furuya , Kazuhisa Okada , Hiroaki Matsui
发明人： Ryoji Furuya , Kazuhisa Okada , Hiroaki Matsui
CPC分类号： H03D3/007 , H03C3/40 , H03D7/1433 , H04B1/406
摘要： The present invention provides a semiconductor integrated circuit for communication (RF IC) realizing high yield without deteriorating a carrier leak characteristic even when a modulation circuit is formed by using cheep parts with large variations. In a semiconductor integrated circuit (RF IC) including: an input circuit constructed by a differential amplifier circuit and a level shifter, which is provided on the ante stage of a mixer of a differential circuit called a Gilbert Cell; and a modulation circuit that performs modulation by adding an I/Q signal and a carrier wave signal, a calibration circuit for canceling a DC offset in an output of the input circuit is provided.
摘要翻译： 本发明提供了一种用于通信（RF IC）的半导体集成电路，即使在通过使用具有大变化的尖峰部分形成调制电路时，也能实现高产率而不劣化载波泄漏特性。 一种半导体集成电路（RF IC），包括：由差分放大电路和电平移位器构成的输入电路，其设置在称为吉尔伯特细胞的差分电路的混频器的前端; 以及通过添加I / Q信号和载波信号来执行调制的调制电路，提供了用于消除输入电路的输出中的DC偏移的校准电路。
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公开(公告)号：US20110053529A1
公开(公告)日：2011-03-03
申请号：US12917135
申请日：2010-11-01
申请人： Ryoji Furuya , Kazuhisa Okada , Hiroaki Matsui
发明人： Ryoji Furuya , Kazuhisa Okada , Hiroaki Matsui
IPC分类号： H04B1/04
CPC分类号： H03D3/007 , H03C3/40 , H03D7/1433 , H04B1/406
摘要： The present invention provides a semiconductor integrated circuit for communication (RF IC) realizing high yield without deteriorating a carrier leak characteristic even when a modulation circuit is formed by using cheep parts with large variations. In a semiconductor integrated circuit (RF IC) including: an input circuit constructed by a differential amplifier circuit and a level shifter, which is provided on the ante stage of a mixer of a differential circuit called a Gilbert Cell; and a modulation circuit that performs modulation by adding an I/Q signal and a carrier wave signal, a calibration circuit for canceling a DC offset in an output of the input circuit is provided.
摘要翻译： 本发明提供了一种用于通信（RF IC）的半导体集成电路，即使在通过使用具有大变化的尖峰部分形成调制电路时，也能实现高产率而不劣化载波泄漏特性。 一种半导体集成电路（RF IC），包括：由差分放大电路和电平移位器构成的输入电路，其设置在称为吉尔伯特细胞的差分电路的混频器的前端; 以及通过添加I / Q信号和载波信号来执行调制的调制电路，提供了用于消除输入电路的输出中的DC偏移的校准电路。
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公开(公告)号：US08315579B2
公开(公告)日：2012-11-20
申请号：US12917135
申请日：2010-11-01
申请人： Ryoji Furuya , Kazuhisa Okada , Hiroaki Matsui
发明人： Ryoji Furuya , Kazuhisa Okada , Hiroaki Matsui
CPC分类号： H03D3/007 , H03C3/40 , H03D7/1433 , H04B1/406
摘要： The present invention provides a semiconductor integrated circuit for communication (RF IC) realizing high yield without deteriorating a carrier leak characteristic even when a modulation circuit is formed by using cheep parts with large variations. In a semiconductor integrated circuit (RF IC) including: an input circuit constructed by a differential amplifier circuit and a level shifter, which is provided on the ante stage of a mixer of a differential circuit called a Gilbert Cell; and a modulation circuit that performs modulation by adding an I/Q signal and a carrier wave signal, a calibration circuit for canceling a DC offset in an output of the input circuit is provided.
摘要翻译： 本发明提供了一种用于通信（RF IC）的半导体集成电路，即使在通过使用具有大变化的尖峰部分形成调制电路时，也能实现高产率而不劣化载波泄漏特性。 一种半导体集成电路（RF IC），包括：由差分放大电路和电平移位器构成的输入电路，其设置在称为吉尔伯特细胞的差分电路的混频器的前端; 以及通过添加I / Q信号和载波信号来执行调制的调制电路，提供了用于消除输入电路的输出中的DC偏移的校准电路。
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公开(公告)号：US20060194606A1
公开(公告)日：2006-08-31
申请号：US11360424
申请日：2006-02-24
申请人： Ryoji Furuya , Kazuhisa Okada , Hiroaki Matsui
发明人： Ryoji Furuya , Kazuhisa Okada , Hiroaki Matsui
CPC分类号： H03D3/007 , H03C3/40 , H03D7/1433 , H04B1/406
摘要： The present invention provides a semiconductor integrated circuit for communication (RF IC) realizing high yield without deteriorating a carrier leak characteristic even when a modulation circuit is formed by using cheep parts with large variations. In a semiconductor integrated circuit (RF IC) including: an input circuit constructed by a differential amplifier circuit and a level shifter, which is provided on the ante stage of a mixer of a differential circuit called a Gilbert Cell; and a modulation circuit that performs modulation by adding an I/Q signal and a carrier wave signal, a calibration circuit for canceling a DC offset in an output of the input circuit is provided.
摘要翻译： 本发明提供了一种用于通信（RF IC）的半导体集成电路，即使在通过使用具有大变化的尖峰部分形成调制电路时，也能实现高产率而不劣化载波泄漏特性。 在一种半导体集成电路（RF IC）中，包括：由差分放大器电路和电平移位器构成的输入电路，其设置在称为吉尔伯特电池的差分电路的混频器的前端上; 以及通过添加I / Q信号和载波信号来执行调制的调制电路，提供了用于消除输入电路的输出中的DC偏移的校准电路。
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