公开(公告)号：US20170288656A1

公开(公告)日：2017-10-05

申请号：US15468025

申请日：2017-03-23

Applicant: SK Hynix Inc. ,  Korea University Research and Business Foundation

Inventor： Jeong CHO ,  Soowon KIM ,  Jinhoon HYUN ,  Chanhui JEONG ,  Daehan KWON

IPC: H03K5/156 ,  H03K5/15

CPC classification number: H03K5/1565 ,  H03K5/15013

Abstract: A device for correcting a multi-phase clock signal includes a first duty ratio adjusting circuit (DRAC) to adjust a duty ratio of a first clock signal; a variable delay line (VDL) delaying a second clock signal; a second DRAC adjusting a duty ratio of the VDL output; first and second differential clock generating circuits (DFCGs) generating differential signals from first and second DRAC outputs, respectively; an edge combining circuit combining edges of outputs from the DFCGs; a duty ratio detecting circuit (DRDC) detecting a duty ratio of a first DRAC output or a first DFCG output in a first mode and of an edge combining circuit output in a second mode; a first control circuit controlling the first and second DRACs using a DRDC output in the first mode; and a second control circuit controlling the VDL using the DRDC output in the second mode.

公开(公告)号：US20240176421A1

公开(公告)日：2024-05-30

申请号：US18524096

申请日：2023-11-30

Applicant: Korea University Research and Business Foundation

Inventor： Seong Whan LEE ,  Ji Won LEE ,  Seo Hyun LEE ,  Soowon KIM ,  Jung Sun LEE

IPC: G06F3/01 ,  G10L15/02 ,  G10L15/18 ,  G10L21/0208

CPC classification number: G06F3/015 ,  G10L15/02 ,  G10L15/18 ,  G10L21/0208 ,  G10L2015/027

Abstract: Disclosed is an apparatus for performance improvement in multimodal communication according to one embodiment of the present invention.